07-19-2020 09:03 PM
I would like to ask a question regarding BUFMR driving 2x BUFIO+BUFR sets of 10-line, 288 MHz DDR LVDS receiver, 6 lines go to one I/O clocking region, 4 lines to another. Each line goes goes through IDELAYE2 and ISERDES (1:8 deserialization, DDR), and clocked by the respective pair of BUFIO+BUFR (BUFR divides by 4 and the clock is 72 MHz).
My question is, are the two clocks from the two BUFRs "perfectly" aligned in phase? i.e. can one of them be selected as a sampling clock that samples all 10 lines (after the ISERDES) without the shallow clock domain crossing?
07-20-2020 07:23 AM - edited 07-20-2020 08:11 AM
So, first, if you are going to do something like this, you need to ensure that the dividers in the BUFR are synchronized. To do this, you need to implement the "BUFR Alignment" procedure documented in Appendix A of UG472 (which may have a problem with the description - I am trying to get it clarified...)
are the two clocks from the two BUFRs "perfectly" aligned in phase?
Nothing is ever "perfectly" aligned in phase, but they are close enough to use synchronous clock crossing techniques (no clock domain crossing circuit is required). The tools understand the potential skew between them and factors that in to the timing analysis.
i.e. can one of them be selected as a sampling clock that samples all 10 lines (after the ISERDES) without the shallow clock domain crossing?
So from a timing analysis point of view, this is true. However, physically it is impossible to clock the CLKDIV of all ISERDES with only one BUFR. The BUFR can only clock resources in the same clock region as the BUFR. If the ISERDES are in two adjacent banks, then, by definition, one BUFR cannot drive the CLKDIV of all BUFR. That being said, the output of the ISERDES can be sampled by either BUFR, so you can bring the 10 bits into one common domain.
But, you need to be careful; by definition, the path between the last FFs (or the ISERDES) that use one BUFR and the first FF that use the other BUFR will be crossing clock regions. If you do this right at the outputs of the ISERDES (which already have a large routing time to get to the fabric), you may have to traverse a significant portion of the height of one clock region in one clock cycle; this can be difficult to get to meet timing - this is compounded by the potential clock skew between the two BUFRs. I would recommend at least one more pipeline stage clocking the bits with the "correct" BUFR before you try to merge them into one.
07-20-2020 07:51 AM - edited 07-20-2020 07:52 AM
Thank you Avrum for, as always, prompt response and to the topic. (the link you shared is not opening)
So first of all, I did put the word "perfect" in quotes and I meant the same
Next, last week I did add a sampling stage at the output of the SERDES prior to "resampling" with the clock that is used down stream *after* I read the BUFR alignment procedure, i.e. I did just what you had suggested but originally I was not planning to do so.
The reason I did it this way was *because* I did review the alignment of the BUFR and I did not like it; specifically, the last bullet in that appendix. It's implying I need another clock for "releasing" the BUFRs but their release will not be synchronized if I use another clock... Unless, I just thought about it... I use the 3rd BUFR with the same clock, since BUFMR can drive up to 3 clocks?