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5,011 Views
Registered: ‎02-14-2017

Clock gating conversion fails

Hi guys,

 

we use Xilinx FPGA (Kintex115) for ASIC prototyping and clock gate conversion is crucial function for us. However, we are not able to force Vivado (2016.2) to use it. Synthesis command is generally as follows: synth_design   -gated_clock_conversion on (or auto). We dont use -flatten_hierarchy none neither keep_hierarchy nor dont_touch attributes. The clock is constrained. Our design is quite complex, in about fifth level module, the clock gate is defined (part of 3d party IP) as:
 
module ClkGate (
CLK,
ClkEnable,
disableg,
GatedClk
);

(* gated_clock = "true" *) input  CLK;            // Un-gated Clock
output GatedClk;       // gated Clock
input  ClkEnable;      // Clock Gating Term
input  disableg;       // Clock Gate Bypass
wire ClkEn;


assign ClkEn = ClkEnable | disableg;
assign GatedClk = CLK & ClkEn;

endmodule;
 
In the synthesis report, I can see the following (+ some other found not-relevant combinational gated clocks):
---------------------------------------------------------------------------------

Start Gated Clock Conversion

---------------------------------------------------------------------------------

Gated Clock Conversion mode: auto

-----------------------------------------------

Starting Gated Clock analysis for module 'XXX_top'

[INFO] Looking for div-by-2 CG opportunities on gated clock '\i_core/CORTEX_CTI/CORTEX/u_etmr4/uEtmR4CORE/GCLK ' 

[INFO] Looking for div-by-2 CG opportunities on gated clock '\i_core/CORTEXR4_CTI/CORTEX/u_etmr4/uEtmR4SOC/GATCLK ' 

[INFO] Found 2 combinational gated clocks in this module ('XXX_top')

End Gated Clock analysis for module 'XXX_top'

-----------------------------------------------




Report Gated Clocks: 

+-+---------------------+-----------+------------+---------+--------+--------+------+

| |Gated Clock net name |Clock Name |Gating Type |#FF/SRLs |#RAMs_A |#RAMs_B |#DSPs |

+-+---------------------+-----------+------------+---------+--------+--------+------+

+-+---------------------+-----------+------------+---------+--------+--------+------+

---------------------------------------------------------------------------------

End Gated Clock Conversion
So, Vivado recognizes the gated clock in some way, but no further operation is made. How to make it working any ideas? Or how to debug why it gives it up?
 
Regards,
Michael
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5 Replies
austin
Scholar
Scholar
4,995 Views
Registered: ‎02-27-2008

Michael,

 

The tool is trying to synthesize to the Xilinx primitives, not your ASIC library.  It cannot recognize what you intend, without some help.

 

In https://www.synopsys.com/company/resources/synopsys-press/fpga-based-prototyping-methodology-manual.html this subject is covered (as well as many more).

 

It is a free download.  Worth your time.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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4,966 Views
Registered: ‎02-14-2017

Hi Austin,

 

thank you for your reply. I understand that Vivado synthesizes to the Xilinx primitives. I expect that if I want to make the design for FPGA. My issue is that I followed all Xilinx instructions (putting in gated_clock = "true" attribute, etc.) regarding synthesis gated_clock_conversion option without any success to see as result any gate conversion (as I described in my first post). Synthesizer still gates the clock with AND followed by BUFG. For the clock gate RTL module provided in the first post, I followed the recommendations given in Application Note from ARM (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0545815/Prototyping_ARM_Cortex_A_Processors_using_FPGA_platforms.pdf).

 

Any ideas?

 

Michael

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gszakacs
Instructor
Instructor
4,942 Views
Registered: ‎08-14-2007

From the messages in your first post, it appears that synthesis is having trouble locating the register that drives the clock enables.  If you want a clock gate pushed into a BUFGCE, the register that creates the gate becomes part of the BUFGCE structure.  If the two gating terms come from registers on different clocks or if they come from somewhere outside the hierarchy being examined by the synthesizer, then the tools may not be able to automatically create the gated clock.  Just taking the gate term as written and using it as the CE input of a BUFGCE would cause a gating delay that doesn't match the RTL.  It also seems that the tools are smart enough to look for other solutions like divide-by-2, but couldn't match those to the RTL, either.

-- Gabor
4,881 Views
Registered: ‎02-14-2017

Thank you Gabor, for your analysis.

 

The gating signal is generated with the same clock which are going to be gated. The gating signal comes from a flip-flop located in one-level lower module within the adjacent module to the ClkGate module.

 

May I help the synthetizer to create in the design flip-flops with enable signal (acting as gate signal) instead of BUFGCE. For example, by moving the gate signal flip-flop on the same hierarchy level or play with -flatten_hierarchy parameter?

 

I know, it can be implemented using BUFG(H)CE, but I would prefer solution with the flip-flop enables for some reasons. Moreover, ARM recommends this kind of solution, so it should be somehow possible in Vivado.

 

Michael

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zhang_shuai@
Visitor
Visitor
971 Views
Registered: ‎02-22-2019

Hi Michael,

What is the result for this issue. Have you resolved it as expected? 

I now meet the same issue. So looking for your help.

Thanks,

Shuai

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