04-08-2019 12:12 AM
I'm working on a design that has the following XDC constraint applied in the user's Target XDC file:
set_output_delay -clock clk_80_out_clock_generator_new 2.500 [get_ports fpga_q*_data*]
After compilation I find the following warning:
[Vivado 12-646] clock 'clk_80_out_clock_generator_new ' not found
The warning points to the line in the XDC file where the "set_ouput_delay" constraint is applied.
This is strange to me because when I run "report_clocks" in the TCL console I clearly see a clock with the same name (clk_80_out_clock_generator_new) as in the XDC command.
So why Vivado wasn't able to find the clock ?
04-08-2019 12:52 AM
Hi, @shaikon ,
1. How is the clock "clk_80_out_clock_generator_new " generated, by user xdc or automatically generated by MMCM?
2. Confirm that set_output_delay constraint is run after clock "clk_80_out_clock_generator_new" has been generated.
04-08-2019 01:18 AM
Hi @shaikon ,
I believe you have multiple user generated .xdc files. And these files have create_clock constraints or generated clock constraints.
This looks like a XDC processing order issue.
Try to set clocks and set basic constraints in one XDC.
Check for more info. UG 903 page 12 onwards, Ordering your constraints. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug903-vivado-using-constraints.pdf
04-08-2019 02:11 PM
This most often happens when the clock in question is generated in an IP block. IP blocks are synthesize out-of-context (OOC) and hence are black boxes when the top level design is synthesized. Since the IP block is not part of the top level synthesis, any clocks generated in an OOC IP do not exist at the time of top level synthesis, and hence any constraints that expect them will result in this error.
However, during place and route (or even when the synthesized top level design is opened) the OOC IP blocks are part of the design, and hence the clocks will exist.
It is important to note that the XDC files are read twice once during synthesis and once at the end of synthesis (after the black boxes have been filled in). This error is probably only occurring on the first one - on the second one, the constraint is being correctly processed.
Take a look at this post on how the XDCs are ready twice.
04-08-2019 03:59 PM
1. How is the clock "clk_80_out_clock_generator_new " generated, by user xdc or automatically generated by MMCM? Automatically.
2. Confirm that set_output_delay constraint is run after clock "clk_80_out_clock_generator_new" has been generated.I confirm.
04-08-2019 06:51 PM
This clock name does not look to be auto-generated by the tool. Can you show us the contents about this generated clock in the "report_clocks" outputs?
And at which stage do you see this warning, in Synthesis or Implementation, or both?
Another way to specify the clock in your set_output_delay constraint is to use [get_clocks -of_objects [get_pins xxxxx]], in which get_pins is to query the pin on which the generated clock is defined.