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Registered: ‎05-03-2018

Closing Timings - Path delays issue

I am having difficulty closing timings due to path delay setup between signals belonging to different clock domains.
I tried to make several changes, without ever being able to close the timings (successfully performing, at the same time, the regression tests that make me consider the design valid at this stage).
In particular, I always have problems on paths concerning resets ...

Currently, the situation is this:

Vivado version: Vivado 2019.2
Project Device: xc7z015clg485-1

Primary clock: FCLK_CLK0 of the ZYNQ (ZYNQ7 Processing System), 100 MHz

Secondary clocks: two clocks, clk_160 and clk_40 of 40 and 160 MHz frequencies (phase 0), both generated by a Clocking Wizard with primary clock as input clock

In block design there is a FIFO (FIFO Generator) with two different clocks:

RD CLK: clk_160


1. Does it make sense to use the interconnect_aresetn asynchronous reset generated by the Vivado Processor System Reset as input reset for FIFO and then enable reset synchronization internally within FIFO? Or is it preferable to synchronize the interconnect_aresetn reset with WR CLK and RD CLK respectively and send the two resulting resets as input to the FIFO (disabling the synchronization function)?

2. There is also a block in the block design, let's call it my_block, which has the three clocks as above and contains several synchronous processes with these clocks. Does it make sense to use the interconnect_aresetn asynchronous reset as the only reset in this block?

3. To all the other blocks of the design, AXI Smart Connect and other AXI peripherals, I send as a reset the peripheral_aresetn generated by the Processor System Reset, which is synchronous with the slowest_sync_clk clock, which in my case is connected to FCLK_CLK0.
Rightly so?

4. Would it be preferable to use other resets?
5. Are there specific constraints for resets (I would like to avoid using the set_false_path)?

NB. To begin with, I am using an empty .xdc with no constraints (the clocks are defined by the xdc that Vivado generates for the ZYNQ Processing system and CLocking Wizard components). Then, getting an error-free timing analysis, I thought about correcting the warnings, inserting the input / output delay.

Thanks in advance,

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