cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
539 Views
Registered: ‎06-15-2018

Coding AXI quad SPI

The AXI Quad SPI IP has and example XDC file shown below (2018.2). As near as I can tell, it seems to be an example in which the IP is configured for a "Frequency Ratio" of 4, but I'm guessing. My frequency ratio is 16 because my SPI device is butt slow.  My question is, how do I determine what changes to make in the highlighted parameters. Some of these are a bit mysterious. for instance the -edges in the example is {3 5 7}. Why is it not {1 3 5}? For my Frequency Ratio 16 case, I'm not sure if I need to make it {3 11 19} or {1 9 17}, or what? Where is this described? 

#####################################################################################################
# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive) #
# as per guidance given in product guide. #
# User should uncomment, update constraints based on board delays and use #
#####################################################################################################

#####################################################################################################
# STARTUPE3 primitive is not used inside the IP #
#####################################################################################################
#### All the delay numbers have to be provided by the user

#### CCLK max delay is 6.7 ns ; refer Data sheet
#### We need to consider the max delay for worst case analysis
##set cclk_delay 6.7

#### Following are the SPI device parameters
#### Max Tco
##set tco_max 7
#### Min Tco
##set tco_min 1
#### Setup time requirement
##set tsu 2
#### Hold time requirement
##set th 3

#### Following are the board/trace delay numbers
#### Assumption is that all Data lines are matched
##set tdata_trace_delay_max 0.25
##set tdata_trace_delay_min 0.25
##set tclk_trace_delay_max 0.2
##set tclk_trace_delay_min 0.2

##### End of user provided delay numbers
##create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}

#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]

#### Data is captured into SPI on the following rising edge of SCK
#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

0 Kudos
0 Replies