cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
1,030 Views
Registered: ‎03-03-2017

Compare timing in 2 different designs

Jump to solution

I am using Vivado 2017.4 and I would like to be able to compare timing on a specific path in 2 different designs.   For example I took the HDMI example design that runs on a KC705 and the design implemented successfully with a WNS of 0.819.   I then took that design, exported the block design and imported that block design into a project I have which uses a slightly smaller Kintex 7 (xc7k160tffg676-1 instead of xc7k325tffg900-2 on the KC705) and when I implement I cannot seem to get past the timing failing.

 

Specifically on the failing design the failing timing is in Intra-Clock Paths, under lclk_from_txpll (Setup) for the following paths:

 

- Source: exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_enc_reg[0][n1qm][1][2]/C

- Destination: exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_disp_reg_reg[1]/D

I am wondering how I can find the timing on that exact same path in the passing design in the KC705 project and see how the two paths compare.   When I open implementation and run timing report I cannot find that path under the lclk_from_txpll (Setup) group since only the 10 worst paths are shown and there are probably thousands of paths in that group.

 

Is there some TCL command I can use to tell it to show me timing on a path where I specify the source and destination?

 

Thanks!

Tim

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
1,418 Views
Registered: ‎01-23-2009

Re: Compare timing in 2 different designs

Jump to solution

I am wondering how I can find the timing on that exact same path in the passing design in the KC705 project and see how the two paths compare. 

 

You can use the Tcl interface to generate a timing report on a specific path. In this case it would be

 

report_timing -from [get_cells exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_enc_reg[0][n1qm][1][2] ] -to [get_cells exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_disp_reg_reg[1] ] -name my_path

 

But, I warn you, this will not likely lead to any meaningful information...

 

Assuming the design can meet timing (which you have shown in one device), the fact that it isn't meeting timing doesn't have anything to do with the failing path. The implementation process is chaotic (see this post on the definition of chaotic)- when you change any input condition (in this case the part) you end up with a completely different solution.

 

The solution in your 2nd device doesn't meet timing. Again, this likely has nothing to do with the failing path. Maybe the device is overfull which is causing timing issues, or maybe this is just the chaos of the system...

 

Fixing designs that are close enough to the edge where the chaos makes a difference is complicated. In ISE we could try a different seed and keep our fingers crossed. In Vivado, there is no seed... You can try a different implementation strategy (more because this is a change in the initial condition than what the change really does), or change the design in some other way. One good bet is to figure out how to reduce the size of your logic - reducing size helps placement, and also changes your initial condition...

 

(There are other ways, but they get increasingly more complex).

 

Avrum

View solution in original post

3 Replies
Highlighted
Guide
Guide
1,419 Views
Registered: ‎01-23-2009

Re: Compare timing in 2 different designs

Jump to solution

I am wondering how I can find the timing on that exact same path in the passing design in the KC705 project and see how the two paths compare. 

 

You can use the Tcl interface to generate a timing report on a specific path. In this case it would be

 

report_timing -from [get_cells exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_enc_reg[0][n1qm][1][2] ] -to [get_cells exdes_wrapper_INST/exdes_i/v_hdmi_tx_ss/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/ENC_INST/clk_disp_reg_reg[1] ] -name my_path

 

But, I warn you, this will not likely lead to any meaningful information...

 

Assuming the design can meet timing (which you have shown in one device), the fact that it isn't meeting timing doesn't have anything to do with the failing path. The implementation process is chaotic (see this post on the definition of chaotic)- when you change any input condition (in this case the part) you end up with a completely different solution.

 

The solution in your 2nd device doesn't meet timing. Again, this likely has nothing to do with the failing path. Maybe the device is overfull which is causing timing issues, or maybe this is just the chaos of the system...

 

Fixing designs that are close enough to the edge where the chaos makes a difference is complicated. In ISE we could try a different seed and keep our fingers crossed. In Vivado, there is no seed... You can try a different implementation strategy (more because this is a change in the initial condition than what the change really does), or change the design in some other way. One good bet is to figure out how to reduce the size of your logic - reducing size helps placement, and also changes your initial condition...

 

(There are other ways, but they get increasingly more complex).

 

Avrum

View solution in original post

Highlighted
1,015 Views
Registered: ‎03-03-2017

Re: Compare timing in 2 different designs

Jump to solution

@avrumw,

   Thanks for the information.   As you can see below, my post-implementation utilization is very low for the device.

   I understand that changing the device is a big variable change.  But for the timing on the path that is failing quite badly, to me it just doesn't make sense, so comparing against a device that does pass will at least give me an idea of what kind of timing that path should be able to achieve (or is possible on that device).

post_impl_utilization.png

   

Thanks.

Tim

0 Kudos
Highlighted
Observer
Observer
930 Views
Registered: ‎08-17-2016

Re: Compare timing in 2 different designs

Jump to solution

*Disclosure - I work for Plunify.

 

I like to add that to trigger the "seeds" behavior in Vivado is quite easy. The link from avrumw contains information on how to do that yourself. You can also use InTime software to do so easily where there is a recipe(tcl script) called "placement exploration". (InTime is a timing optimization software. Plunify is a Xilinx alliance partner -  https://www.xilinx.com/alliance/memberlocator/1-5r4474.html)

We have seen optimization between 200ps to 500ps off your WNS, without any changes to your design. So it is quite a useful approach if you are at the last mile of your work. 

 

----------------------------------------------------
InTime - Timing Optimization with ML (Blog)
0 Kudos