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Anonymous
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Constraining 4:1 Clock MUX

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Hi all,

I have a clock structure in Ultra-scale as shown in the figure. ( To implement this clock structure, I had to give clock dedicated route= false constraint). 

 

I gave below constraints.

 

create_generated_clock -name BUFGCTRL1_0 -divide_by 1 -source [get_pins BUFGCTRL1/I0] [get_pins BUFGCTRL1/O]
create_generated_clock -name BUFGCTRL1_1 -divide_by 1 -source [get_pins BUFGCTRL1/I1] [get_pins BUFGCTRL1/O] -master_clock [get_clocks mmcm2_clk_out] -add

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL1_0] -group [get_clocks BUFGCTRL1_1]

 

create_generated_clock -name BUFGCTRL2_0 -divide_by 1 -source [get_pins BUFGCTRL2/I0] [get_pins BUFGCTRL2/O]
create_generated_clock -name BUFGCTRL2_1 -divide_by 1 -source [get_pins BUFGCTRL2/I1] [get_pins BUFGCTRL2/O] -master_clock [get_clocks mmcm3_clk_out] -add

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL2_0] -group [get_clocks BUFGCTRL2_1]

 

create_generated_clock -name BUFGCTRL3_0 -divide_by 1 -source [get_pins BUFGCTRL3/I0] [get_pins BUFGCTRL3/O]
create_generated_clock -name BUFGCTRL3_1 -divide_by 1 -source [get_pins BUFGCTRL3/I1] [get_pins BUFGCTRL3/O] -master_clock [get_clocks mmcm4_clk_out] -add
set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL3_0] -group [get_clocks BUFGCTRL3_1]

 

But BUFGCTRL3_1 clock is showing inter clock violation with all other generated clocks except  BUFGCTRL3_0. 

 

Is this the intended behavior? 

Why can't vivado identify it as a 4:1 clock MUX and exclude all clocks interaction between each other even if logically exclude constraints were applied (to each MUX separately though).

Is there any way I can give constraints better?

 

Regards

Anoop

4_1_clk_mux_new_arch.jpg
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Guide
Guide
4,909 Views
Registered: ‎01-23-2009

So this is different than the structure you showed before, and is slightly more complicated.

 

I am actually surprised that the constraints were allowed - I would have thought there would be a problem with them...

 

In spite of the fact that you declare BUFGCTRL1_0 and BUFGCTRL_1 as exclusive, they both still exist on BUFGCTRL2/I0. As a result, I am surprised that the create_generated_clock BUFGCTRL2_0 passes, since the -source pin has two clocks on it.

 

Next, what are we trying to accomplish here - is this really just a 4:1 MUX, or are there any other loads on the outputs of the intermetdiate BUFGMUXes (i.e. on BUFGMUX2_0? If this is just a 4:1 MUX, then...

 

First, this structure is inefficient - the cascading of the MUXes makes the MUX very unbalanced. It would be better to MUX MMCM1 with MMCM2, and MMCM3 with MMCM4, then MUX the outputs of the two first level MUXes. Not only does this make the clocks more balanced, it also makes the constraints a bit simpler.

 

I will assume this is the case.

 

First create the generated clocks for the outputs of the two "first level" BUFGMUXes. For MMCM1 and MMCM2 use the create_generated_clock commands that you have for BUFGCTRL1_0 and BUFGCTRL1_1. Do the same for MMCM3 and MMCM4, generating (say) BUFGCTRL2_0 and BUFCTRL2_1.

 

Now we have 4 clocks. If the only place these 4 clocks go is out through the output of the last MUX (taking the inputs from the other 2 MUXes), then these 4 clocks are mutually exclusive, and you can constrain them in one command

 

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL1_0] -group [get_clocks BUFGCTRL1_1] -group [get_clocks BUFGCTRL2_0] -group [get_clocks BUFGCTRL2_1]

 

(there is no need to create new generated clocks on the output of the 2nd stage MUX - it just carries all 4 of the generated clocks).

 

Avrum

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Voyager
Voyager
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Registered: ‎06-24-2013

Hey @Anonymous,

 

To implement this clock structure, I had to give clock dedicated route= false constraint

Not good :)

 

Is there any way I can give constraints better?

Did you consider building only a two level deep MUX structure?

I.e. MUX1 for MMCM1 and MMCM2, MUX2 for MMCM3 and MMCM4 and MUX3 for MUX1 and MUX2?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Anonymous
Not applicable
3,666 Views

@hpoetzl

Thanks for the quick reply's.

 

To implement this clock structure, I had to give clock dedicated route= false constraint

Not good :)

 I know. Want to avoid it. But  I want to get some answers/clarifications etc.

 

Did you consider building only a two level deep MUX structure?

Yes. I could constraint First two MUXs (mmcm1 , mmcm2 & mmcm3, mmcm4). But I could not create a generated clock at I1 input of third MUX. Because I need to give a master clock for that pin. There is no existing master clock for that pin. Any suggestion?

 

Regads

Anoop

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Moderator
Moderator
3,629 Views
Registered: ‎11-09-2015

Hi @Anonymous,

 

The correct constraints when muxing clocks are set_clocks_groups or set_false_path.

 

The set_clocks_groups command defines which clocks are related to each other. All combinations of clocks belonging to different groups are considered to be unrelated, and hence all paths between them are declared false.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Anonymous
Not applicable
3,627 Views

Hi @florentw,

Thanks for the reply.

What I understood from Forum discussions and user guides, it is advisable to give exclusive constraints to clock MUXes. 

 

Are you suggesting to give false path for clock MUXes generally or specific to my structure?

 

Regards

Anoop

 

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Highlighted
Guide
Guide
4,910 Views
Registered: ‎01-23-2009

So this is different than the structure you showed before, and is slightly more complicated.

 

I am actually surprised that the constraints were allowed - I would have thought there would be a problem with them...

 

In spite of the fact that you declare BUFGCTRL1_0 and BUFGCTRL_1 as exclusive, they both still exist on BUFGCTRL2/I0. As a result, I am surprised that the create_generated_clock BUFGCTRL2_0 passes, since the -source pin has two clocks on it.

 

Next, what are we trying to accomplish here - is this really just a 4:1 MUX, or are there any other loads on the outputs of the intermetdiate BUFGMUXes (i.e. on BUFGMUX2_0? If this is just a 4:1 MUX, then...

 

First, this structure is inefficient - the cascading of the MUXes makes the MUX very unbalanced. It would be better to MUX MMCM1 with MMCM2, and MMCM3 with MMCM4, then MUX the outputs of the two first level MUXes. Not only does this make the clocks more balanced, it also makes the constraints a bit simpler.

 

I will assume this is the case.

 

First create the generated clocks for the outputs of the two "first level" BUFGMUXes. For MMCM1 and MMCM2 use the create_generated_clock commands that you have for BUFGCTRL1_0 and BUFGCTRL1_1. Do the same for MMCM3 and MMCM4, generating (say) BUFGCTRL2_0 and BUFCTRL2_1.

 

Now we have 4 clocks. If the only place these 4 clocks go is out through the output of the last MUX (taking the inputs from the other 2 MUXes), then these 4 clocks are mutually exclusive, and you can constrain them in one command

 

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL1_0] -group [get_clocks BUFGCTRL1_1] -group [get_clocks BUFGCTRL2_0] -group [get_clocks BUFGCTRL2_1]

 

(there is no need to create new generated clocks on the output of the 2nd stage MUX - it just carries all 4 of the generated clocks).

 

Avrum

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Anonymous
Not applicable
3,598 Views

@avrumw

 

(there is no need to create new generated clocks on the output of the 2nd stage MUX - it just carries all 4 of the generated clocks).

This was the answer I was looking for. Thanks a lot. It helped me.

 

Actually my first design was a two stage MUX. But I was in the presumption that every Clock MUX inputs needs to be constrained. That is why I changed it to a three stage MUX and produced generated clocks for each MUX inputs.

 

Regards

Anoop

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