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Observer ugompper
Observer
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Registered: ‎08-22-2018

Constraining Center-Aligned Dual Data Rate with Souce Synchronous differential Inputs @60MHz

Hello,

I am trying to setup the correct constraints for a 12-Bit ADC (LTC2263-12) that is sending these 12 bits on two lanes with dual data rate (DDR) at a 20MHz sampling rate. There is also a bit clock and a frame clock. The data is center-aligned and I am trying to capture it statically on a zynq with -1C Speed Grade which gives a window of -0.38/1.85 for setup and hold.

I found this post, which is quite similar to my problem and was solved. The problem I have is that the data sheet of the ADC does not give setup and hold time and instead provides DATA to DCO Delay with minimum and maximum values. If I try to translate these values to the constraints file my timing failes (WNS: -9.163 ns and TNS: -72.091 ns).

 

timing2.png

 

timing.png

 

At 20MHz sampling rate and Two Lanes, 12-Bit Serialization, I get:

t_SER=8.333
t_DATA=2.917 (min) and 5.417 (max)

and I guess I also have to include Output Rise and Output Fall Time into my calculations (which I didn't do, because I don't know how):

t_R=0.17
t_F=0.17

 

Given those numbers I thought my windows for capturing would look like the following (wrt. the post mentioned above):

- Window -1: Centered around the falling edge before the first rising edge (at t=-8.333)

- starts at t=-11.25, ends at t=-5.417

- Window 0: Centered around the first rising edge (at t=0.0)

- starts at t=-2.917, ends at t=2.917

- Window 1: Centered around the first falling edge (at t=8.333)

- starts at t=5.417, ends at t=11.249

- Window 2: Centered around the second rising edge (at t=16.666)

- starts at t=13.749, ends at t=19.582

 

With this timing it should be possible to capture each window with the clock edge around which it is centered, even without adding a delay.


Taken these numbers I came up with the following contraints which failed timing:

 

#### ADC Pins ####
set_property IOSTANDARD LVDS_25 [get_ports {OUTB_IN_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {DCO_IN_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {OUTA_IN_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {FR_IN_clk_p[0]}]
set_property PACKAGE_PIN M17 [get_ports {OUTB_IN_clk_p[0]}]
set_property PACKAGE_PIN H16 [get_ports {DCO_IN_clk_p[0]}]
set_property PACKAGE_PIN F16 [get_ports {OUTA_IN_clk_p[0]}]
set_property PACKAGE_PIN J18 [get_ports {FR_IN_clk_p[0]}]

#### Clock Pins from the ADC #### create_clock -period 16.667 -name DCO -waveform {0.000 8.333} [get_ports {DCO_IN_clk_p[0]}] # Bit Clock for the Data (60 MHz) create_clock -period 50.000 -name FR -waveform {0.000 25.000} [get_ports {FR_IN_clk_p[0]}] # Frame Clock (20 MHz) create_clock -period 16.667 -name DCO_virtual # virtual clock is needed for constraining the delay (60 MHz) set_input_jitter DCO 0.060 # Jitter of the Bit Clock set_false_path -setup -rise_from [get_clocks DCO_virtual] -fall_to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] set_false_path -setup -fall_from [get_clocks DCO_virtual] -rise_to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] set_false_path -hold -rise_from [get_clocks DCO_virtual] -rise_to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] set_false_path -hold -fall_from [get_clocks DCO_virtual] -fall_to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] set_multicycle_path -setup -from [get_clocks DCO_virtual] -to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] 0 set_multicycle_path -hold -from [get_clocks DCO_virtual] -to [get_clocks -include_generated_clocks -of [get_ports DCO_IN_clk_p[0]]] -1 set_input_delay -clock DCO_virtual -2.917 -max [get_ports OUTA_IN_clk_p[0]] set_input_delay -clock DCO_virtual -2.917 -max [get_ports OUTB_IN_clk_p[0]] set_input_delay -clock DCO_virtual -5.417 -min [get_ports OUTA_IN_clk_p[0]] set_input_delay -clock DCO_virtual -5.417 -min [get_ports OUTB_IN_clk_p[0]] set_input_delay -clock DCO_virtual -2.917 -max [get_ports OUTA_IN_clk_p[0]] -clock_fall -add_delay set_input_delay -clock DCO_virtual -2.917 -max [get_ports OUTB_IN_clk_p[0]] -clock_fall -add_delay set_input_delay -clock DCO_virtual -5.417 -min [get_ports OUTA_IN_clk_p[0]] -clock_fall -add_delay set_input_delay -clock DCO_virtual -5.417 -min [get_ports OUTB_IN_clk_p[0]] -clock_fall -add_delay set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets clk]

I don't know if it is at any interest, but both clocks (DCO and FR) and the data lines (OUTA and OUTB) come in differential pairs so I connected them inside the Diagram with Utility Buffers set to IBUFDS (C size: 1).

 

diff.png

 

 

Thank you

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