UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
428 Views
Registered: ‎10-07-2016

Constraining oddr output interface properly

Jump to solution

Dear Xilinx members,

I have a question about the correct constraining of the following, blue highlighted circuit:

Pic1.JPG

I want to implement a dual data rate output interface on a Kintex7 XC7K160T-2FFG676 device, by using the HR-Banks (no odelays available). The output data at "dout" shall appear center aligned to the output clock named "clk_out_p/n" (source synchronous interface). The attached device is a dvi transmitter, which has the following requiremetns:

Tsetup = 0.6ns; Thold = 0.5ns; Fclkmax = 165MHz.

In order to provide the output data "dout" center aligned to the output clock "clk_out_p/n", I have instantiated a MMCM named "INST_CLK_WIZ_0", which creates the two clocks:

clk_out1 = clock with 0° phase shift

clk_out2 = clock with 90° phase shift.

So I clock out the data with clk_out1 by using an ODDR, while the clock output signal "clk_out_p/n" is generated, by using an ODDR, whose clock input is driven by the clk_out2 (90° phaswe shifted clock).

The MMCM block looks like in the following picture:

Pic2.JPG

Can anybody give me a hint how to constrain this design properly?

Kind regards

stgateizo

0 Kudos
1 Solution

Accepted Solutions
Historian
Historian
294 Views
Registered: ‎01-23-2009

Re: Constraining oddr output interface properly

Jump to solution

Why does the tool refer to the wrong clock source, and why can the correct clock source not be adjusted? Is this a bug?

No idea. I don't use the wizards. It is definitely wrong, and, from what you have shown, it doesn't appear to be operator error (but I don't know if you are showing all the steps). If that's the case, then its just a bug.

Avrum

0 Kudos
4 Replies
Historian
Historian
384 Views
Registered: ‎01-23-2009

Re: Constraining oddr output interface properly

Jump to solution

The constraints for an output interface are pretty much always the same - the set_output_delay -max is the setup requirement of your external device and the set_output_delay -min is the negative of your hold.

But you need to reference them to the proper clock, which in a source synchronous interface is a generated clock at the output of your device.

I will assume that your input clock (clk_in_p) is properly constrained...

So first, you need to define the generated clock for the output clock

create_generated_clock -name clk_fwd -source [get_pins INST_ODDR_CLK/C] -divide_by 1 [get_ports clk_out_p]

Next you need to define the normal output constraints

set_output_delay -clock clk_fwd 0.6 [get_ports dout]
set_output_delay -clock clk_fwd -min -0.5 [get_ports dout]
set_output_delay -clock clk_fwd 0.6 [get_ports dout] -clock_fall -add_delay
set_output_delay -clock clk_fwd -min -0.5 [get_ports dout] -clock_fall -add_delay

The mechanism you are using (with an MMCM with with a 90 degree phase shift, and using the ODDRs) is the right way to do what you are trying to do.

The only other subtlety is the MMCM. For the timing engine to properly understand this 90 degree phase shift the MMCM PHASESHIFT_MODE must be in WAVEFORM mode - this is required so that the tool will choose the right edges for timing the interface. In all devices prior to UltraScale+ this is the default. In UltraScale+ the default was changed to LATENCY mode, which is incorrect for this usage. So when you create your clock wizard core, be sure to select WAVEFORM mode (take a look at this post on setting the PHASESHIFT_MODE in the clocking wizard).

Highlighted
Explorer
Explorer
366 Views
Registered: ‎10-07-2016

Re: Constraining oddr output interface properly

Jump to solution

Hello avrumw,

thank you very much for this helpful information. It's clear now, how I need to constrain the design (by the way, yes the clk_in_p is constrainted by using a correpsonding create_clock constraint).

I have one additional question:

When I use the Timing Constraints Wizard (in Vivado under implementation) to define the constraints for the ddr output interface, I would expect that the constarints created by the Timing Constraints Wizard would result in the same constraints as the constraints, which you suggested in your last post.

So I opened the Timing Constraints Wizard, and check marked the forwarded clock as suggested by the tool. So far so good.

Pic1.JPG

Then, I tried to understand the suggested constraint for the output delays. The tool refers to clk_in_p instead to the previous created forwarded clock clk_out_p!!!
The set_output_delay constraints which you have suggested, refer to the clk_out_p, which makes sense from my point of view. So I assume that the Timing Constranits Wizard refers here to a wrong clock source. Unfortunately, I can even not change the reference clock in the tool.

Why does the tool refer to the wrong clock source, and why can the correct clock source not be adjusted? Is this a bug?

Pic2.JPG

Kind regards

stgateizo

0 Kudos
Historian
Historian
295 Views
Registered: ‎01-23-2009

Re: Constraining oddr output interface properly

Jump to solution

Why does the tool refer to the wrong clock source, and why can the correct clock source not be adjusted? Is this a bug?

No idea. I don't use the wizards. It is definitely wrong, and, from what you have shown, it doesn't appear to be operator error (but I don't know if you are showing all the steps). If that's the case, then its just a bug.

Avrum

0 Kudos
Explorer
Explorer
275 Views
Registered: ‎10-07-2016

Re: Constraining oddr output interface properly

Jump to solution

Hello avrumw,

actually the timing wizard is a nice tool, which shows you things which are not constrained, or which should be constrained. But it really seems like a bug.

Thank you for this info.

Best regards

0 Kudos