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Observer g.pavlikh
Observer
1,356 Views
Registered: ‎09-10-2012

Constraint dual-purpose pin

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In my project I have dual-purpose input pin. In one case it is clock, in other - it is data bit on different clock.
Simplified layout is in attached picture.test.png

For timing I use these constraints:

create_clock -period 7.400 -name CHAN_A_CLK [get_ports {ChA_CLK}]
create_clock -period 7.400 -name CHAN_B_CLK [get_ports {ChB_CLK_ChA_D2}]

set_clock_groups -asynchronous -group [get_clocks CHAN_A_CLK] -group [get_clocks CHAN_B_CLK]

create_clock -period 7.400 -name VIRTUAL_DATA_CLK -waveform {0.000 3.700}
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -min 1.5 -add_delay [get_ports {ChA_D1}]
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -max 5.9 -add_delay [get_ports {ChA_D1}]
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -min 1.5 -add_delay [get_ports {ChB_CLK_ChA_D2}]
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -max 5.9 -add_delay [get_ports {ChB_CLK_ChA_D2}]
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -min 1.5 -add_delay [get_ports {ChB_D1}]
set_input_delay -clock [get_clocks {VIRTUAL_DATA_CLK}] -max 5.9 -add_delay [get_ports {ChB_D1}]

In my idea I want to use clock CHAN_A_CLK for A1 and A2 flip-flops analyze and CHAN_B_CLK for B1 flip-flop analyze.

In timing report after implementation I expect to see this interractions:
1. from ChA_D1 (VIRTUAL_DATA_CLK) to A1 (CHAN_A_CLK).
2. from ChB_CLK_ChA_D2 (VIRTUAL_DATA_CLK) to A2 (CHAN_A_CLK).
3. from ChB_D1 (VIRTUAL_DATA_CLK) to B1 (CHAN_B_CLK).

But in reality there are only 1 and 3.
What need I to modify in constraints to improve timing analyze?

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1 Solution

Accepted Solutions
Observer g.pavlikh
Observer
1,195 Views
Registered: ‎09-10-2012

Re: Constraint dual-purpose pin

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Some experiments shown that order of contstraints is the thing.

If set_input_delay is declared before create_clock on the same pin - both constraints are used and no WARNING: [Constraints 18-96] is generatted.

Unfournately, timing on this path doesn't met because router uses fast clock line both for data and clock path, but it is another story.

 

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6 Replies
Scholar drjohnsmith
Scholar
1,343 Views
Registered: ‎07-09-2009

Re: Constraint dual-purpose pin

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Before you constrain from / to,
does the thing synthesis / P&R

The tools are quiet strict about clocks being used as clock and data , as clock and data are very different routes in the chip.

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Observer g.pavlikh
Observer
1,335 Views
Registered: ‎09-10-2012

Re: Constraint dual-purpose pin

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Yes, P&R is fine. There are CLOCK_DEDICATED_ROUTE on clock B path and no flip-flops in IO buffers.
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Historian
Historian
1,303 Views
Registered: ‎01-23-2009

Re: Constraint dual-purpose pin

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There are a couple of "odd" things about your constraints, but nothing that I see that shouldn't work...

How are you determining that the constraint on A2_reg is not working?

The two odd things are:

  • You are using a virtual clock for the set_input_delays. This isn't necessary - you could use CHAN_A_CLK for ChA_D1 and ChA_D2 and CHAN_B_CLK for ChB_D1
  • You should not have the -add_delay on any of these constraints - these are the only constraints (one min and one max) on these pins, and hence should not have the -add_delay

But neither of these things should be a problem for the constraints...

What do you get when you do

report_timing -to [get_cells A2_reg]

Avrum

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Historian
Historian
1,302 Views
Registered: ‎01-23-2009

Re: Constraint dual-purpose pin

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and no flip-flops in IO buffers

In fact, there is no problem using the IOB flip-flops. The IOB has two paths from the IBUF - one directly to the IOB flip-flop/IDDR/ISERDES (either directly or through the IDELAY) and one directly to the fabric. The tools can use both at the same time, so it would use the internal path for the IOB FF and the fabric path for routing to the BUFG.

Avrum

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Observer g.pavlikh
Observer
1,289 Views
Registered: ‎09-10-2012

Re: Constraint dual-purpose pin

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I'll remove -add_delay from constraint set, thanks for pointing on this issue.

Odd things came from the whole design:
1. There are 16 of similar parts with two clocks, so virtual clock is for simplicity - I need only one declaration for min/max delay instead of 16.
2. No flip-flops in IOB - because there are some pins that feed two FFs with different clocks at the same time. Just for sameness.

How do I determine that the constraint on A2_reg is not working? In my design there are 16 bits in "ChA" instead of 2 as on picture. After P&R in Timing report in Inter-Clock Paths section I see group VIRTUAL_DATA_CLK to CHAN_A_CLK with 15 endpoints, the only one missing in pin that shared with clock.

And I just noticed warnings that (as I understood) explain the issue:
WARNING: [Constraints 18-96] Setting input delay on a clock pin is not supported, ignoring it
Observer g.pavlikh
Observer
1,196 Views
Registered: ‎09-10-2012

Re: Constraint dual-purpose pin

Jump to solution

Some experiments shown that order of contstraints is the thing.

If set_input_delay is declared before create_clock on the same pin - both constraints are used and no WARNING: [Constraints 18-96] is generatted.

Unfournately, timing on this path doesn't met because router uses fast clock line both for data and clock path, but it is another story.

 

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