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Explorer
Explorer
6,520 Views
Registered: ‎07-20-2009

Constraints for clock structure

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Hello all,

Please check the attached file. I have a circuit similar to that in FPGA. I am facing timing violations (especially clock skew) in the clock domain given to the logic represented as clouds. Please suggest some timing constraints or modifications in clock circuit for better timing.

 

Inputs

1. Device is Kintex Ultra-scale. All clocks (CLK1-CLK4) are input to FPGA and have same frequency. All the MMCM have same configuration.

2. For BUFGCTRL, dynamic clock switching is not intended.

3. two modes of operations are possible mode1: SEL1=SEL2=SEL3=SEL4=0 , Mode2: SEL1=0, SEL2=SEL3=SEL4=1

4. CLK1 & CLK2 IOs are in lower half. Others are in upper half

4. For all MMCM-BUFGCTRL-BUFG combination, pblocks are assigned to separate clock regions(two in upper half, two in lower half).

 

questions

1. Is there any logically/physically exclusive constraints needed for BUFGCTRLs?

2. Is there any better modification for the circuit?

 

 

clk_mux.jpg
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Historian
Historian
10,314 Views
Registered: ‎01-23-2009

Re: Constraints for clock structure

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So, first, a BUFGCTRL is a BUFG, and hence you don't need (in fact should not use) a second BUFG after each BUFGCTRL.

 

Second, the BUFGCTRL is considered a buffer to the static timing engine. As a result, it propagates the clocks through the BUFGCTRLs, So the outputs of each of the BUFGCTRLs have both clocks on them. For example, the top BUFGCTRL output (CLK1_i) has CLK1 and CLK2 (or the versions of them generated by the MMCM) on it.

 

If left alone, any path that is clocked (on both ends) by the net CLK1_i, will actually be 4 paths

  - CLK1 -> CLK1

  - CLK2 -> CLK2

  - CLK1 -> CLK2

  - CLK2 -> CLK1

 

Clearly the last two are impossible and incorrect, and hence an exception is needed.

 

The big question is "do these clocks go anywhere else other than the inputs to the BUFGCTRLs" - i.e. is there any logic connected to the clocks before the BUFGCTRLs.

 

If these clocks only go to the BUFGCTRL inputs (and no other logic) then they are logically exclusive, and can be declared as such. This is (pretty much the only) case for using the set_clock_groups command. Again, if these clocks go no where other than the BUFGMUXes, then you can use the command

 

set_clock_groups -logically_exclusive  \

  - group [get_clocks -of_objects [get_pins <mmcm1>/CLKOUT0] \

  - group [get_clocks -of_objects [get_pins <mmcm3>/CLKOUT0]

 

set_clock_groups -logically_exclusive  \

  - group [get_clocks -of_objects [get_pins <mmcm1>/CLKOUT0] \

  - group [get_clocks -of_objects [get_pins <mmcm4>/CLKOUT0]

 

However, the last ones are problematic. You have two BUFGMUXes, each choosing either CLK1 or CLK2. How do these two interact? I presume since there are two of them, there is the possibility that one of them chooses CLK1 and the other chooses CLK2 (otherwise you would only need one). If that is the case, then we have to worry about the possibility of paths between CLK_1i and CLK2_i - if one exists, and CLK1_i selects CLK1 and CLK2_i selects CLK2, then CLK1 and CLK2 cannot be declared logically exclusive.

 

So in this case (or in the case that the clocks go places other than the inputs of the BUFGMUX, then we need to get fancier.

 

We need to distinguish the clocks that exist before the BUFGCTRLs from the clocks that exist after the BUFGCTRLs. This is done with create_generated_clocks. I will only do the commands for BUFGCTRL_1 - the other ones will need the same constraints

 

create_generated_clock -name BUFGCTRL1_0 -divide_by 1 -source [get_pins BUFGCTRL1/I0] [get_pins BUFGCTRL1/O]

create_generated_clock -name BUFGCTRL1_1 -divide_by 1 -source [get_pins BUFGCTRL1/I1] [get_pins BUFGCTRL1/O] -add

 

Be very careful with the -add option - the first one must not have the -add and the second one must have it.

 

Now we have declared two new clocks, BUFGCTRL1_0 and BUFGCTL1_1. These clocks are on the same pin, so it is safe to declare them as logically exlusive. This does not however declare CLK1 and CLK2 logically exclusive (which is what we want).

 

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL1_0] -group [get_clocks BUFGCTRL1_1]

 

Avrum

 

18 Replies
Scholar embedded
Scholar
6,500 Views
Registered: ‎06-09-2011

Re: Constraints for clock structure

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@anoopjoseph,

When you generate a clock inside FPGA you should use create_generated_clock constraint. for clock dividers or clock mux you need to define this constraint. This should be done for 4 outputs of the BUFGCTRLi. Look at the UG903 for a complete information regarding this issue.

As all clocks going out of MMCM/PLL would be constrained automatically by the tool, I would prefer to place BUFGCTRL before MMCM. Just try it and see if it improves timing results.

 

Hope this will help,

Hossein

 

Moderator
Moderator
6,487 Views
Registered: ‎09-15-2016

Re: Constraints for clock structure

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Hi @anoopjoseph

 

As correctly mentioned by @embedded, you need to write the generated clock on the outputs of all BUFGMUX w.r.t source clock. After that logically exclusive constraints has to be written to tell the timing engine that one clock needs to be propagated at one instant.

Refer UG903, page 43:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug903-vivado-using-constraints.pdf

 

Regards

Rohit

Regards
Rohit
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Moderator
Moderator
6,484 Views
Registered: ‎11-04-2010

Re: Constraints for clock structure

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Hi, @anoopjoseph,
1. As Hossein mentioned, you only need to create_clock on the 4 input clock ports(CLK1~CLK4).
2. The clock on the output of MMCM will be automatically derived. (You can use report_clocks command to get the all the clock information).
3. When generating MMCM in IP catalog, confirm no BUFG is used in the output clock.
4. No need to craete_genetated_clock for the output of BUFGCTRL.
5. You should set physically exclusive between 2 input clocks of BUFGCTRL.
6. Why do you add BUFG after BUFGCTRL?

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Scholar embedded
Scholar
6,464 Views
Registered: ‎06-09-2011

Re: Constraints for clock structure

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@hongh,

 

Not sure but, I doubt if the tool can constrain BUFGCTRL ourput !. So, we need to define that constraint - craete_genetated_clock - for it!.

 

Hossein

Historian
Historian
10,315 Views
Registered: ‎01-23-2009

Re: Constraints for clock structure

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So, first, a BUFGCTRL is a BUFG, and hence you don't need (in fact should not use) a second BUFG after each BUFGCTRL.

 

Second, the BUFGCTRL is considered a buffer to the static timing engine. As a result, it propagates the clocks through the BUFGCTRLs, So the outputs of each of the BUFGCTRLs have both clocks on them. For example, the top BUFGCTRL output (CLK1_i) has CLK1 and CLK2 (or the versions of them generated by the MMCM) on it.

 

If left alone, any path that is clocked (on both ends) by the net CLK1_i, will actually be 4 paths

  - CLK1 -> CLK1

  - CLK2 -> CLK2

  - CLK1 -> CLK2

  - CLK2 -> CLK1

 

Clearly the last two are impossible and incorrect, and hence an exception is needed.

 

The big question is "do these clocks go anywhere else other than the inputs to the BUFGCTRLs" - i.e. is there any logic connected to the clocks before the BUFGCTRLs.

 

If these clocks only go to the BUFGCTRL inputs (and no other logic) then they are logically exclusive, and can be declared as such. This is (pretty much the only) case for using the set_clock_groups command. Again, if these clocks go no where other than the BUFGMUXes, then you can use the command

 

set_clock_groups -logically_exclusive  \

  - group [get_clocks -of_objects [get_pins <mmcm1>/CLKOUT0] \

  - group [get_clocks -of_objects [get_pins <mmcm3>/CLKOUT0]

 

set_clock_groups -logically_exclusive  \

  - group [get_clocks -of_objects [get_pins <mmcm1>/CLKOUT0] \

  - group [get_clocks -of_objects [get_pins <mmcm4>/CLKOUT0]

 

However, the last ones are problematic. You have two BUFGMUXes, each choosing either CLK1 or CLK2. How do these two interact? I presume since there are two of them, there is the possibility that one of them chooses CLK1 and the other chooses CLK2 (otherwise you would only need one). If that is the case, then we have to worry about the possibility of paths between CLK_1i and CLK2_i - if one exists, and CLK1_i selects CLK1 and CLK2_i selects CLK2, then CLK1 and CLK2 cannot be declared logically exclusive.

 

So in this case (or in the case that the clocks go places other than the inputs of the BUFGMUX, then we need to get fancier.

 

We need to distinguish the clocks that exist before the BUFGCTRLs from the clocks that exist after the BUFGCTRLs. This is done with create_generated_clocks. I will only do the commands for BUFGCTRL_1 - the other ones will need the same constraints

 

create_generated_clock -name BUFGCTRL1_0 -divide_by 1 -source [get_pins BUFGCTRL1/I0] [get_pins BUFGCTRL1/O]

create_generated_clock -name BUFGCTRL1_1 -divide_by 1 -source [get_pins BUFGCTRL1/I1] [get_pins BUFGCTRL1/O] -add

 

Be very careful with the -add option - the first one must not have the -add and the second one must have it.

 

Now we have declared two new clocks, BUFGCTRL1_0 and BUFGCTL1_1. These clocks are on the same pin, so it is safe to declare them as logically exlusive. This does not however declare CLK1 and CLK2 logically exclusive (which is what we want).

 

set_clock_groups -logically_exclusive -group [get_clocks BUFGCTRL1_0] -group [get_clocks BUFGCTRL1_1]

 

Avrum

 

Moderator
Moderator
6,421 Views
Registered: ‎11-04-2010

Re: Constraints for clock structure

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Hi, @embedded,

Both input clocks of BUFGCTRL can propagate through it.

You can see 2 clocks on the output of BUFGCTRL with the below command:

%get_clocks -of  [get_pins BUFGCTRL1/O]

 

 

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Explorer
Explorer
6,413 Views
Registered: ‎07-20-2009

Re: Constraints for clock structure

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Hi 

 

 

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Moderator
Moderator
6,410 Views
Registered: ‎11-04-2010

Re: Constraints for clock structure

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Hi, @anoopjoseph,

If the clock before BUFGCTRL does not drive any other logic, there is no need to create_generated_clock for the BUFGCTRL 's output.

 

 

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Historian
Historian
6,407 Views
Registered: ‎01-23-2009

Re: Constraints for clock structure

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The second solution I proposed (with the create_generated_clocks) is always valid for a clock MUX - it can be used any time you have a clock MUX, regardless of whether the clocks go only to the MUX or go other places as well.

 

The first solution is an "easier" solution when the clocks go only to the MUX.

 

In your case, you can use the 3 commands (two create_generated_clock and one set_clock_groups) for each of the 4 BUFGCTRLs.

 

Avrum

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Explorer
Explorer
5,564 Views
Registered: ‎07-20-2009

Re: Constraints for clock structure

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Hi hongh,

Thanks for the advice.

 

When I gave first two commands, 

create_generated_clock -name BUFGCTRL1_0 -divide_by 1 -source [get_pins BUFGCTRL1/I0] [get_pins BUFGCTRL1/O]

create_generated_clock -name BUFGCTRL1_1 -divide_by 1 -source [get_pins BUFGCTRL1/I1] [get_pins BUFGCTRL1/O] -add

 

(Opened synthesized design and gave in TCL window )

Following error message displayed. 

"Cannot specify -add without specifying -master_clock".

Any idea which clock I missed? Since the input is from MMCM, master clock should be present right?

 

Regards

Anoop

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Moderator
Moderator
5,557 Views
Registered: ‎11-04-2010

Re: Constraints for clock structure

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Hi, @anoopjoseph ,
You can find the MMCM's output clock with the below command:
get_clocks -of [get_pins MMCM/O]

The exmaple:
create_generated_clock -name BUFGCTRL1_1 -divide_by 1 -source [get_pins BUFGCTRL1/I1] [get_pins BUFGCTRL1/O] -master_clock [get_clocks -of [get_pins MMCM2/CLKOUT1]] -add
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Explorer
Explorer
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Registered: ‎07-20-2009

Re: Constraints for clock structure

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Thanks.

That means -master option needs to be added only along with second create generated clock command ? (the one with -add option?).

 

Regards

Anoop

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Moderator
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Registered: ‎11-04-2010

Re: Constraints for clock structure

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Hi, @anoopjoseph ,
Yes.

Please check the result with report_clocks command in TCL console.
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Explorer
Explorer
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Registered: ‎07-20-2009

Re: Constraints for clock structure

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Hi 

 

 

 

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Explorer
Explorer
5,507 Views
Registered: ‎07-20-2009

Re: Constraints for clock structure

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Hi 

 

 

 

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Historian
Historian
5,495 Views
Registered: ‎01-23-2009

Re: Constraints for clock structure

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You have to show us a failing path (the detailed timing report).

 

From what you have shown us, and assuming the constraints are done right, then there should be no paths between the generated clocks and the master clocks. The first create_generated_clock without the -add "replaces" the master clock downstream from the BUFGCTRL, so the master should end at that point.

 

However, if there are paths from before the BUFGCTRL to after the BUFGCTRL, then you have real timing paths there. Furthermore, the BUFGCTRL introduces significant delay, so the path can have hold time problems.

 

Also, if there are paths from "before" the BUFGCTRL, how are the un-muxed clocks buffered? You need to show us the real clock toplogy - ideally from the schematic generated by the tool, that shows all the clock buffers for (at least) one pair of clocks. If the clock architecture is incorrect (buffers not where they should be), then you will have timing problems.

 

Avrum

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Explorer
Explorer
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Registered: ‎07-20-2009

Re: Constraints for clock structure

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Hi 

 

 

 

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Historian
Historian
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Registered: ‎01-23-2009

Re: Constraints for clock structure

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No.