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linkaiyu
Adventurer
Adventurer
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Registered: ‎03-09-2013

Constraints hierarchy

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Hi!

 

After importing example design files of an IP core, I added a Top Module (named MAIN) to the project.

I have now warnings during implementation, saying that a certain constraint cannot be found, eg:

 

WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_mdio"              =
   PERIOD "mdio_logic" "TS_clock_generator_clkout1" * 40 PRIORITY 0;>
   [ipcore_dir/MAC/example_design/MAC_example_design.ucf(298)]: This constraint
   will be ignored because the relative clock constraint named
   'TS_clock_generator_clkout1' was not found.

 

How do I specify the new relative position of the constrained object?

 

Thank you!

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vemulad
Xilinx Employee
Xilinx Employee
23,039 Views
Registered: ‎09-20-2012

Hi,

 

See the below messages in the .bld file

 

So it says it generated the constraints TS_MAC_design_wrapper_clock_generator_clkout1 and TS_MAC_design_wrapper_clock_generator_clkout1.

 

As you have added the top level file MAC_design_wrapper the constraint name generated has this name appended at its front.

 

So replace the TS_clock_generator_clkout0 with TS_MAC_design_wrapper_clock_generator_clkout0 and TS_clock_generator_clkout1  wiith TS_MAC_design_wrapper_clock_generator_clkout1 in the UCF.

 

replace the clock_generator_clkout0 with MAC_design_wrapper_clock_generator_clkout0 and clock_generator_clkout1  wiith MAC_design_wrapper_clock_generator_clkout1 in the UCF.

 

Hope this helps.

 

Thanks,

Deepika.

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT1: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout1 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout1" TS_clk_in_p / 0.5 HIGH 50%
   INPUT_JITTER 50 ps>

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT0: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout0 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout0" TS_clk_in_p / 0.625 HIGH 50%
   INPUT_JITTER 50 ps>
Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
14,888 Views
Registered: ‎09-20-2012

Hi,

 

This warning says that it is not able to find period constraint defined by name "TS_clock_generator_clkout1".

 

Ensure that you have a constraint which defines the timespec "TS_clock_generator_clkout1"(something like below in UCF).

 

TIMESPEC TS_clock_generator_clkout1 = PERIOD “clk_in” 10ns;

 

You can open technology schematic query for the net name (clk_in) and use the same net hierarchy in the UCF or you can use a wild card entry at the start of net name as below.

 

TIMESPEC TS_clock_generator_clkout1 = PERIOD “*clk_in” 10ns;

 

WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_mdio"              =
   PERIOD "mdio_logic" "TS_clock_generator_clkout1" * 40 PRIORITY 0;>
   [ipcore_dir/MAC/example_design/MAC_example_design.ucf(298)]: This constraint
   will be ignored because the relative clock constraint named
   'TS_clock_generator_clkout1' was not found.
Thanks,
Deepika.
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linkaiyu
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Registered: ‎03-09-2013

Hi!

 

I didn't modify any of the example design files, infact the implementation run successfully without the MAIN module that I added.

i would like to know how to query for the net name in technology schematic.

I double clicked on View Technology Schematic and a window pop out asking me

 

1) start with the explorer wizard

2) start with a schematic of the to-level block

 

then what shall I do to look the net hierarchy?

 

Thank you! 

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vemulad
Xilinx Employee
Xilinx Employee
14,877 Views
Registered: ‎09-20-2012

Hi,

 

Choose "Explorer wizard" and write the net name in search box press enter. Select desired net and click on add. (You can see the complete hierarchy of net here). click on Create Schematic to see the connectivity.

 

Thanks,

Deepika.

Thanks,
Deepika.
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linkaiyu
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Registered: ‎03-09-2013

Hi!

 

Sorry but it can't find any net named like the one in the warning.

You can see the hierarchy in the screenshot.

 

image.jpg

 

# the part selection and associated pin choices (if any) are intended as 
# an example for the family selected.  Please refer to the User Guide
# for more information about IO selection.
# part selected is spartan6 xc6slx45tfgg484
CONFIG PART = xc6slx45tfgg484-3;

#
####
#######
##########
#############
#################
## System level constraints

########## GMII LOC CONSTRAINTS ##########
########## SP605 Board ##########
NET  clk_in_p        LOC = K21  | IOSTANDARD = LVDS_25  | DIFF_TERM = TRUE;
NET  clk_in_n        LOC = K22  | IOSTANDARD = LVDS_25  | DIFF_TERM = TRUE;

Net glbl_rst         LOC = H8   | IOSTANDARD = LVCMOS15 | TIG;

#### Module LEDs_8Bit constraints
Net frame_error      LOC = D17  | IOSTANDARD = LVCMOS25;
Net frame_errorn     LOC = AB4  | IOSTANDARD = LVCMOS25;
Net activity_flash   LOC = D21  | IOSTANDARD = LVCMOS25;
Net activity_flashn  LOC = W15  | IOSTANDARD = LVCMOS25;

#### Module Push_Buttons_4Bit constraints
Net update_speed     LOC = F3   | IOSTANDARD = LVCMOS15;
Net config_board     LOC = G6   | IOSTANDARD = LVCMOS15;
Net pause_req_s      LOC = F5   | IOSTANDARD = LVCMOS15;
Net reset_error      LOC = C1   | IOSTANDARD = LVCMOS15;

#### Module DIP_Switches_4Bit constraints
Net mac_speed<0>     LOC = C18  | IOSTANDARD = LVCMOS25;
Net mac_speed<1>     LOC = Y6   | IOSTANDARD = LVCMOS25;
Net gen_tx_data      LOC = W6   | IOSTANDARD = LVCMOS25;
Net chk_tx_data      LOC = E4   | IOSTANDARD = LVCMOS25 | TIG;

Net phy_resetn       LOC = J22  | IOSTANDARD = LVCMOS25 | TIG;

Net gmii_rxd<7>      LOC = U22  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<6>      LOC = V21  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<5>      LOC = V22  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<4>      LOC = W20  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<3>      LOC = W22  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<2>      LOC = Y21  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<1>      LOC = Y22  | IOSTANDARD = LVCMOS25;
Net gmii_rxd<0>      LOC = P19  | IOSTANDARD = LVCMOS25;

Net gmii_txd<7>      LOC = W12  | IOSTANDARD = LVCMOS25;
Net gmii_txd<6>      LOC = Y12  | IOSTANDARD = LVCMOS25;
Net gmii_txd<5>      LOC = Y9   | IOSTANDARD = LVCMOS25;
Net gmii_txd<4>      LOC = AB9  | IOSTANDARD = LVCMOS25;
Net gmii_txd<3>      LOC = AA8  | IOSTANDARD = LVCMOS25;
Net gmii_txd<2>      LOC = AB8  | IOSTANDARD = LVCMOS25;
Net gmii_txd<1>      LOC = T10  | IOSTANDARD = LVCMOS25;
Net gmii_txd<0>      LOC = U10  | IOSTANDARD = LVCMOS25;


Net gmii_tx_en       LOC = T8   | IOSTANDARD = LVCMOS25;
Net gmii_tx_er       LOC = U8   | IOSTANDARD = LVCMOS25;
Net gmii_tx_clk      LOC = AB7  | IOSTANDARD = LVCMOS25;

Net gmii_rx_dv       LOC = T22  | IOSTANDARD = LVCMOS25;
Net gmii_rx_er       LOC = U20  | IOSTANDARD = LVCMOS25;
Net gmii_rx_clk      LOC = P20  | IOSTANDARD = LVCMOS25;

Net mdc              LOC = R19  | IOSTANDARD = LVCMOS25;
Net mdio             LOC = V20  | IOSTANDARD = LVCMOS25;

Net mii_tx_clk       LOC = L20  | IOSTANDARD = LVCMOS25;

# lock to unused header 
Net serial_response  LOC = A20  | IOSTANDARD = LVCMOS25;
Net tx_statistics_s  LOC = B20  | IOSTANDARD = LVCMOS25;
Net rx_statistics_s  LOC = A19  | IOSTANDARD = LVCMOS25;


#
####
#######
##########
#############
#################
#EXAMPLE DESIGN CONSTRAINTS

############################################################
# Clock Period Constraints                                 #
############################################################


############################################################
# RX Clock period Constraints                              #
############################################################
# Receiver clock period constraints: please do not relax
NET "gmii_rx_clk"                TNM_NET  = "clk_rx_int";
TIMESPEC "TS_rx_clk"       = PERIOD "clk_rx" 8000 ps HIGH 50 %;

NET "*/rx_mac_aclk_int"          TNM_NET  = "clk_rx";
############################################################
# TX Clock period Constraints                              #
############################################################
# Transmitter clock period constraints: please do not relax
NET "clk_in_p" TNM_NET = "clk_in_p";
TIMESPEC "TS_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;

#set to use clock backbone - this uses a long route to allow the MMCM to be placed in the other half of the device
NET "clk_in_p" CLOCK_DEDICATED_ROUTE = BACKBONE;

NET "*/gtx_clk_bufg" TNM_NET = "clk_gtx";
TIMESPEC "TS_gtx_clk"      = PERIOD "clk_gtx" 8000 ps HIGH 50 %;

NET "*tx_mac_aclk*"              TNM_NET  = "clk_tx_mac";
TIMESPEC "TS_tx_clk_gmii"  = PERIOD "clk_tx_mac" 8000 ps HIGH 50 %;

############################################################
# AXI-Lite Clock period Constraints                        #
############################################################
# ignore timing from gtx_clk to the cpu clock
TIMESPEC "TS_glbl_rst" = FROM "clock_generator_clkout0" TO "clock_generator_clkout1" TIG;


#
####
#######
##########
#############
#################
#AXI4-STREAM FIFO CONSTRAINTS

############################################################
# FIFO Clock Crossing Constraints                          #
############################################################

## TX Client FIFO
# Group the clock crossing signals into timing groups
INST "*user_side_FIFO/tx_fifo_i/rd_tran_frame_tog"              TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO/tx_fifo_i/rd_addr_txfer*"                 TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO/tx_fifo_i/rd_txfer_tog"                   TNM = "tx_fifo_rd_to_wr";

INST "*user_side_FIFO/tx_fifo_i/wr_frame_in_fifo"               TNM = "tx_fifo_wr_to_rd";

TIMESPEC "TS_tx_fifo_rd_to_wr"   = FROM "tx_fifo_rd_to_wr" TO "clk_gtx" 7800 ps DATAPATHONLY;
TIMESPEC "TS_tx_fifo_wr_to_rd"   = FROM "tx_fifo_wr_to_rd" TO clk_tx_mac 7800 ps DATAPATHONLY;

# Reduce clock period to allow for metastability settling time

# constrain the input to this register - this is a multicycle path due to the
# resync of the control
INST "*user_side_FIFO/tx_fifo_i/rd_addr_txfer*"                 TNM = "tx_addr_rd";
INST "*user_side_FIFO/tx_fifo_i/wr_rd_addr*"                    TNM = "tx_addr_wr";

TIMESPEC "TS_tx_fifo_addr"       = FROM "tx_addr_rd" TO "tx_addr_wr" 10ns;


## RX Client FIFO
# Group the clock crossing signals into timing groups
INST "*user_side_FIFO/rx_fifo_i/wr_store_frame_tog"             TNM = "rx_fifo_wr_to_rd";
INST "*user_side_FIFO/rx_fifo_i/rd_addr*"                       TNM = "rx_fifo_rd_to_wr";

TIMESPEC "TS_rx_fifo_wr_to_rd"   = FROM "rx_fifo_wr_to_rd" TO "clk_gtx" 7800 ps DATAPATHONLY;
TIMESPEC "TS_rx_fifo_rd_to_wr"   = FROM "rx_fifo_rd_to_wr" TO "clk_rx" 7800 ps DATAPATHONLY;




#
####
#######
##########
#############
#################
#BLOCK CONSTRAINTS

############################################################
# External GMII Constraints                                #
############################################################

# GMII Transmitter Constraints:  place flip-flops in IOB
INST "*trimac_block*gmii_interface*gmii_txd*"                     IOB = true;
INST "*trimac_block*gmii_interface*gmii_tx_en"                    IOB = true;
INST "*trimac_block*gmii_interface*gmii_tx_er"                    IOB = true;

# GMII Receiver Constraints:  place flip-flops in IOB
INST "*trimac_block*gmii_interface*rxd_to_mac*"                   IOB = true;
INST "*trimac_block*gmii_interface*rx_dv_to_mac"                  IOB = true;
INST "*trimac_block*gmii_interface*rx_er_to_mac"                  IOB = true;

############################################################
# The following are required to maximise setup/hold        #
############################################################

INST "gmii_txd*"                                                SLEW = FAST;
INST "gmii_tx_en"                                                 SLEW = FAST;
INST "gmii_tx_er"                                                 SLEW = FAST;
INST "gmii_tx_clk"                                                SLEW = FAST;



############################################################
# GMII: IODELAY Constraints
############################################################
# Please modify the value of the IDELAY_VALUE
# according to your design.
# For more information on IDELAYCTRL and IODELAY, please
# refer to the Spartan-6 User Guide.
#
INST "*trimac_block*gmii_interface*delay_gmii_rx_dv"              IDELAY_VALUE = 25;
INST "*trimac_block*gmii_interface*delay_gmii_rx_er"              IDELAY_VALUE = 25;
INST "*trimac_block*gmii_interface*delay_gmii_rxd"                IDELAY_VALUE = 25;

INST *trimac_block*gmii_interface*bufio_gmii_rx_clk               LOC = BUFIO2_X3Y12;
#INST *trimac_block*gmii_interface*bufg_gmii_rx_clk                LOC = BUFGMUX_X3Y5;
#INST *trimac_block*clock_inst*BUFGMUX_SPEED_CLK                   LOC = BUFGMUX_X3Y13;

############################################################
# For Setup and Hold time analysis on GMII inputs          #
############################################################

# Identify GMII Rx Pads only.  
# This prevents setup/hold analysis being performed on false inputs,
# eg, the configuration_vector inputs.
INST "gmii_rxd*"  TNM = IN_GMII; 
INST "gmii_rx_er" TNM = IN_GMII;
INST "gmii_rx_dv" TNM = IN_GMII;

# The following constraints work in conjunction with IDELAY_VALUE settings to
# check that the GMII receive bus remains in alignment with the rising edge of
# GMII_RX_CLK, to within 2.7ns setup time and 50ps hold time. In addition to
# adjusting IDELAY_VALUE settings for your system's timing characteristics, you
# may wish to refine these constraints to match the GMII specification
# Note that implementation of the GMII physical interface on 
# Spartan-6 devices will not meet the GMII receiver timing specification; 
# see the provided data sheet and Answer Record 35336 on xilinx.com for details.
TIMEGRP "IN_GMII" OFFSET         = IN  2.6 ns VALID 2.7 ns BEFORE "gmii_rx_clk"; 



#
####
#######
##########
#############
#################
#CORE CONSTRAINTS



############################################################
# Crossing of Clock Domain Constraints: please do not edit #
############################################################
# Flow Control logic reclocking - control sugnal is synchronised
INST "*trimac_core*FLOW*PAUSE_REQ_TO_TX*"                        TNM="flow_rx_to_tx";
INST "*trimac_core*FLOW*PAUSE_VALUE_TO_TX*"                      TNM="flow_rx_to_tx";
TIMESPEC "TS_flow_rx_to_tx"      = FROM "flow_rx_to_tx" TO clk_tx_mac 7800 ps DATAPATHONLY;

# generate a group of all flops NOT in the axi clock domain
TIMEGRP "ffs_except_axi"        = FFS EXCEPT "clock_generator_clkout1" "mdio_logic";
TIMESPEC "TS_config_to_all"      = FROM "clock_generator_clkout1" TO "ffs_except_axi" TIG;


# Ignore stats serialiser clock crossing as handled by toggle sync
INST "*x_stats_shift*"                                           TNM="sync_ok";
TIMESPEC "TS_rxstats_sync" = FROM "clk_rx" TO "sync_ok"          TIG;
TIMESPEC "TS_txstats_sync" = FROM "clk_tx_mac" TO "sync_ok"      TIG;

# Ignore pause deserialiser as only present to prevent logic stripping
INST "*/pause_val*"                                                TNM="pause_dsr";
INST "pause_req*"                                                TNM="pause_dsr";
TIMESPEC "TS_pause_dsr" = FROM "pause_dsr"                       TIG;


# add a pin tig on the bufgmux as we always follow a speed change with a reset
# also do not want to time to the select
PIN "*clock_inst*bufgmux_speed_clk.I1" TIG;



############################################################
# Ignore paths to resync flops
############################################################
INST "*/data_sync"                                                TNM = "resync_reg";
INST "*/reset_sync*"                                              TNM = "resync_reg";
TIMESPEC "ts_resync_flops"       = TO "resync_reg" TIG;


############################################################
# MDIO Constraints: please do not edit                     #
############################################################
# Place the MDIO logic in it's own timing groups
INST "*trimac_core*MANIFGEN*ENABLE_REG*"                          TNM = "mdio_logic";
INST "*trimac_core*MANIFGEN*READY_INT*"                           TNM = "mdio_logic";
INST "*trimac_core*MANIFGEN*STATE_COUNT*"                         TNM = FFS "mdio_logic";
INST "*trimac_core*MANIFGEN*MDIO_TRISTATE*"                       TNM = "mdio_logic";
INST "*trimac_core*MANIFGEN*MDIO_OUT*"                            TNM = "mdio_logic";

TIMESPEC "TS_mdio"              = PERIOD "mdio_logic" "TS_clock_generator_clkout1" * 40 PRIORITY 0;

 

Where is the problem? Thank you!!

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vemulad
Xilinx Employee
Xilinx Employee
14,841 Views
Registered: ‎09-20-2012

Hi,

 

TIMESPEC "TS_mdio"  = PERIOD "mdio_logic"  "TS_clock_generator_clkout1" * 40 PRIORITY 0;

 

Here you have mentioned that the period value is 40 times the TS_clock_generator_clkout1 but you didnot specify TS_clock_generator_clkout1 for the tool to calculate the period value.

 

For the above constraint to be valid, there should be a TIMESPEC defined with name "TS_clock_generator_clkout1". I didnot find this TIMESPEC constraint in the UCF you pasted.

 

If you have a MMCM/DCM in the design and you have placed a period constraint on its clock input then the tool automatically generated the period constraints on its outputs. There will be messages like below during translate

 

ConstraintSystem:178 - TNM 'XLXN_1', used in period specification 'TS_XLXN_1', was traced into DCM_SP instance XLXI_1. The following new TNM groups and period specifications were generated at the DCM_SP output(s):
CLK0: <TIMESPEC TS_XLXN_5 = PERIOD "XLXN_5" TS_XLXN_1 HIGH 50%>

 

You can use these auto generated constraints(TS_XLXN_5) in the UCF even with out defining them again in UCF.

 

Please check in .bld report if there are any INFO messages like above. 

 

Else create a TIMESPEC for "TS_clock_generator_clkout1" and then use it in related constraint.

 

Check page-18 "Manually related synchronus clock domains" section of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/ug612.pdf

 

Can you attach the ISE project archive so that I can check this further?

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
14,833 Views
Registered: ‎09-20-2012

Hi,

 

I suspect that may be you have placed PERIOD constraint on MMCM/DCM input which was taken correctly and PERIOD constraints are generated on outputs earlier. But now may be this period constraint on MMCM input is not being taken by tool correctly. Can you check this? Can you attach .bld report file?

 

Thanks,

Deepika.

Thanks,
Deepika.
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siktap
Scholar
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14,813 Views
Registered: ‎06-14-2012

Moving to Timing

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linkaiyu
Adventurer
Adventurer
14,795 Views
Registered: ‎03-09-2013

Thank you Vemulad for the help!

Here is the .bld and the full project.

 

 

Release 14.5 ngdbuild P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -sd ipcore_dir -nt timestamp -uc CONSTRAINTS.ucf -p
xc6slx45t-fgg484-3 MAIN.ngc MAIN.ngd

Reading NGO file "C:/Users/Kaiyu/Desktop/MAC AXI4/MAC/MAIN.ngc" ...
Loading design module "ipcore_dir/MAC.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "CONSTRAINTS.ucf" ...
INFO:coreutil - Full license for component <tri_mode_eth_mac> allows you to use
   this component. This license does not give you access to source code
   implementing this component.

INFO:coreutil - Full license for component <tri_mode_eth_mac> allows you to use
   this component. This license does not give you access to source code
   implementing this component.

Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_glbl_rst" = FROM
   "clock_generator_clkout0" TO "clock_generator_clkout1" TIG;>
   [CONSTRAINTS.ucf(127)]: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'clock_generator_clkout0'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_glbl_rst" = FROM
   "clock_generator_clkout0" TO "clock_generator_clkout1" TIG;>
   [CONSTRAINTS.ucf(127)]: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'clock_generator_clkout1'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "ffs_except_axi"        = FFS
   EXCEPT "clock_generator_clkout1" "mdio_logic";> [CONSTRAINTS.ucf(265)]:
   Unable to find an active 'TNM' or 'TimeGrp' constraint named
   'clock_generator_clkout1'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_config_to_all"      =
   FROM "clock_generator_clkout1" TO "ffs_except_axi" TIG;>
   [CONSTRAINTS.ucf(266)]: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'clock_generator_clkout1'.

WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_mdio"              =
   PERIOD "mdio_logic" "TS_clock_generator_clkout1" * 40 PRIORITY 0;>
   [CONSTRAINTS.ucf(304)]: This constraint will be ignored because the relative
   clock constraint named 'TS_clock_generator_clkout1' was not found.

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT1: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout1 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout1" TS_clk_in_p / 0.5 HIGH 50%
   INPUT_JITTER 50 ps>

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT0: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout0 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout0" TS_clk_in_p / 0.625 HIGH 50%
   INPUT_JITTER 50 ps>

Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   5

Total memory usage is 166964 kilobytes

Writing NGD file "MAIN.ngd" ...
Total REAL time to NGDBUILD completion:  15 sec
Total CPU time to NGDBUILD completion:   14 sec

Writing NGDBUILD log file "MAIN.bld"...

 

Thank you again!

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vemulad
Xilinx Employee
Xilinx Employee
23,040 Views
Registered: ‎09-20-2012

Hi,

 

See the below messages in the .bld file

 

So it says it generated the constraints TS_MAC_design_wrapper_clock_generator_clkout1 and TS_MAC_design_wrapper_clock_generator_clkout1.

 

As you have added the top level file MAC_design_wrapper the constraint name generated has this name appended at its front.

 

So replace the TS_clock_generator_clkout0 with TS_MAC_design_wrapper_clock_generator_clkout0 and TS_clock_generator_clkout1  wiith TS_MAC_design_wrapper_clock_generator_clkout1 in the UCF.

 

replace the clock_generator_clkout0 with MAC_design_wrapper_clock_generator_clkout0 and clock_generator_clkout1  wiith MAC_design_wrapper_clock_generator_clkout1 in the UCF.

 

Hope this helps.

 

Thanks,

Deepika.

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT1: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout1 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout1" TS_clk_in_p / 0.5 HIGH 50%
   INPUT_JITTER 50 ps>

INFO:ConstraintSystem:178 - TNM 'clk_in_p', used in period specification
   'TS_clk_in_p', was traced into PLL_ADV instance PLL_ADV. The following new
   TNM groups and period specifications were generated at the PLL_ADV output(s):
    
   CLKOUT0: <TIMESPEC TS_MAC_design_wrapper_clock_generator_clkout0 = PERIOD
   "MAC_design_wrapper_clock_generator_clkout0" TS_clk_in_p / 0.625 HIGH 50%
   INPUT_JITTER 50 ps>
Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
9,333 Views
Registered: ‎09-20-2012

Hi,

 

Here is the modified UCF file which passes translate. Use this file in your ISE project and re-run implementation.

 

Cheers,

Deepika.

Thanks,
Deepika.
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quantumfuture
Visitor
Visitor
9,227 Views
Registered: ‎01-09-2014

I'm trying the solution provided here with PlanAhead, but the problem is that PlanAhead preprocess the contraints file before the translate phase and since it does not find the *_clock_generator_clkout0 and *_clock_generator_clkout2 timespec (that are generated during the translate phase) it ignores the TS_clock_path_gtx2ref timespec.

Any solution to this?

 

I've attached a screenshot of the PlanAhead messages.

screen_20140109-120038.png
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