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pulsar
Explorer
Explorer
434 Views
Registered: ‎04-16-2015

Constraints_problem

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Hello all

I use following:

process (ADC_FRAME_CLK)
begin
if (ADC_FRAME_CLK'event and ADC_FRAME_CLK='1') then
REG_ADC_8(13) <= Ch8_A_shift_13;
REG_ADC_8(12) <= Ch8_A_shift_12;
...............................
REG_ADC_8(1) <= Ch8_A_shift_1;
REG_ADC_8(0) <= Ch8_A_shift_0;
end if;
end process;

And I want to use constraint for them:
set_max_delay -datapath_only -from [get_pins Ch8_A_shift_0_reg/Q] -to [get_pins REG_ADC_8_reg[0]/D] 2.200

I found these pins in Tcl:
request:
get_pins Ch8_A_shift_0_reg/Q
reply:
Ch8_A_shift_0_reg/Q

request:
get_pins REG_ADC_8_reg[0]/D
reply:
REG_ADC_8_reg[0]/D


But Implementation gives critical warning:
[Constraints 18-515] set_max_delay: Path segmentation by forcing 'Ch8_A_shift_0_reg/Q' to be timing startpoint. [E:/VICT/Vivado2017_3/ADC_FMC_8ch_DMA_China_K325__14_W/PCIe_DMA_KC705__v23.srcs/constrs_1/imports/PCIe_DMA_KC705__v23_11_2/constrs.xdc:84]
Resolution: Use valid startpoint to avoid path segmentation such as the clock pin of a register.

Please help me understand the problem and avoid the critical warning.

Thank you.
Best regards,
Viktor
P.S.
I worked in Vivado2017.3

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1 Solution

Accepted Solutions
dsheils
Moderator
Moderator
218 Views
Registered: ‎01-05-2017

 Hi @pulsar 

I took a quick look through your design. You have 2 external clocks coming into your design and internally you are using them to pass data from one clock domain to the other. You don't seem to be using any clock domain synchronisation circuitry. You need to include such a mechanism.

You also have put a set_false_path between the 2 domains. This is telling Vivado that you don't care about about any timing paths between the 2 domains when clearly you do. Please get rid of this constraint.

You need to:

1. Implement a clock domain crossing circuit so that data is passed safely from one domain to the next.

2. Apply appropriate constraints after the above is done. This will probably involve set_max_delay -datapath and async_reg property.

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6 Replies
dsheils
Moderator
Moderator
432 Views
Registered: ‎01-05-2017

Hi @pulsar 

You need to set the constraint on the clock pin of the starting register:

set_max_delay -datapath_only -from [get_pins Ch8_A_shift_0_reg/C] -to [get_pins REG_ADC_8_reg[0]/D] 2.200

However set_max_delay -datapath_only is generally only used to constrain a path on a clock domain crossing.

 

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pulsar
Explorer
Explorer
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Registered: ‎04-16-2015

Hi, @dsheils

Thank you for your reply.

There are two important circumstances:
1)
Signals
Ch8_A_shift_0
and
REG_ADC_8(0)
were strobed with the different clock domain, defined as:
create_clock -period 3.57 -name FMC_HPC_CLK0_M2C_P -add [get_ports FMC_HPC_CLK0_M2C_P]
set_input_jitter FMC_HPC_CLK0_M2C_P 0.010

create_clock -period 6.25 -name FMC_HPC_CLK1_M2C_P -add [get_ports FMC_HPC_CLK1_M2C_P]
set_input_jitter FMC_HPC_CLK1_M2C_P 0.010

And these clock are asynchronous.
It was defined as:

set_clock_groups -name async_clk0_clk1 -asynchronous -group [get_clocks -include_generated_clocks FMC_HPC_CLK0_M2C_P] -group [get_clocks -include_generated_clocks FMC_HPC_CLK1_M2C_P] -group [get_clocks -include_generated_clocks CLK_EXTERNAL_P]

2)
Constraints

set_max_delay -datapath_only -from [get_pins Ch8_A_shift_0_reg/C] -to [get_pins REG_ADC_8_reg[0]/D] 0.001

was successfully completed with the Implementation.

It looks impossible due to delay = 1ps.

Could you explain this result to me?

Thank you.
Best regards,
Viktor

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dsheils
Moderator
Moderator
343 Views
Registered: ‎01-05-2017

Hi @pulsar 

A few things:

1. Why do you have the -add on the create_clock constraints? Do you already have another clock constraint created on this pin? If not, then the -add is not needed.

2. You are using the set_clock_groups -asynchonrous constraint and then further on you are using set_max_delay. Be aware that the set_clock_groups constraint will override any other constraint on these paths including the set_max_delay constraint. You should see a warning about this in the Report_Methodology. By using the set_clock_groups -async you are basically telling the tool to put a false path between these clock domains. However in your case it seems that you have paths between these clock domains and if that is true then using the set_clock_groups -async is incorrect here and can result in failure. Instead we need to have proper clock domain crossing circuitry and the correct constraints, typically using the set_max_delay -datapath.

3.  The value of 1ps for the set_max_delay -datapath doesnt make sense. The appropriate value for the set_max_delay -datapath_only depends on what kind of clock crossing you are doing. Usually its less than the source clock period but it really depends on the clock domain crossing circuit.

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pulsar
Explorer
Explorer
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Registered: ‎04-16-2015

Hi, @dsheils

I have made simple design and I ask you to look 2 files in the attachment.

Project have 2 clocks.
Definition in the constraint file :

# ADC_BIT_CLK_P Fmax.bit = 280 MHz
create_clock -period 3.570 -name FMC_HPC_CLK0_M2C_P [get_ports FMC_HPC_CLK0_M2C_P]
set_input_jitter FMC_HPC_CLK0_M2C_P 0.010

# ADC_FRAME_CLK_P Fmax,frame = 160 MHz
create_clock -period 6.250 -name FMC_HPC_CLK1_M2C_P [get_ports FMC_HPC_CLK1_M2C_P]
set_input_jitter FMC_HPC_CLK1_M2C_P 0.010

I do not know in advance their mutual positions in the timing diagram (it is adjusted in the clock signal source)

So, these are asynchronous clocks and first time Implementaion gave critical warning:
"Timing constraint are not met"
After that I did following:
tools -> timing -> report clock interaction ->
chose red -> chose set false_path

and software added this line into constraints.xdc:

set_false_path -from [get_clocks FMC_HPC_CLK0_M2C_P] -to [get_clocks FMC_HPC_CLK1_M2C_P]


Then I added 2 lines into constraints.xdc:
set_max_delay -datapath_only -from [get_ports FMC_HPC_LA32_P] -to [get_cells Ch8_A_shift_*] 2.200

set_max_delay -datapath_only -from [get_pins Ch8_A_shift_0_reg/C] -to [get_pins {REG_ADC_8_reg[0]/D}] 0.001

As a result
set_max_delay -datapath_only -from [get_ports FMC_HPC_LA32_P] -to [get_cells Ch8_A_shift_*] 2.200
works properly (delay less than 2.200 will give critical warning),

but
set_max_delay -datapath_only -from [get_pins Ch8_A_shift_0_reg/C] -to [get_pins {REG_ADC_8_reg[0]/D}] 0.001
did not give critical warning, so this constraint do not works.

Now Synthesis and Implementation do not give any error and warning.

I think I do not understand how to limit the datapath only
from output of
Ch8_A_shift_0
to input of
REG_ADC_8(0)
in this simple design.


Please help.

Thank you.
Best regards,
Viktor

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dsheils
Moderator
Moderator
219 Views
Registered: ‎01-05-2017

 Hi @pulsar 

I took a quick look through your design. You have 2 external clocks coming into your design and internally you are using them to pass data from one clock domain to the other. You don't seem to be using any clock domain synchronisation circuitry. You need to include such a mechanism.

You also have put a set_false_path between the 2 domains. This is telling Vivado that you don't care about about any timing paths between the 2 domains when clearly you do. Please get rid of this constraint.

You need to:

1. Implement a clock domain crossing circuit so that data is passed safely from one domain to the next.

2. Apply appropriate constraints after the above is done. This will probably involve set_max_delay -datapath and async_reg property.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

pulsar
Explorer
Explorer
202 Views
Registered: ‎04-16-2015

Hi,   dsheils

I did not make Implementation of  a clock domain crossing circuit and do not know how to do it.

Please suggest where can I read about this method ?

Thank you

regards,

Viktor

 

 

 

 

 

 

 

 
 
 
 
 
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