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Visitor
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Registered: ‎08-10-2016

Critical Path calculation via SERDES in multi-FPGA

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Hello,

Calculating Critical path delay of a design in multi-FPGA environment, includes on-chip computation delay and off-chip communication delays (I/O pin delay + trace delay).

My question is that , if two FPGAs are connected via SERDES modules, will the critical path calculation  include the I/OSERDES module delays as well other than the I/O pin delays and trace delays ?

 

Thanks

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Guide
Guide
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Registered: ‎01-23-2009

When one talks about "critical path", one is talking about a static timing path that comes closest to violating (or violates by the most) the static timing requirement of the path.

 

In a single FPGA, the critical path may be internal (from a clocked resource inside the FPGA to another clocked resource inside the FPGA), or partly external;

  - an input path; from an input pin to an internal clocked element

  - an output path; from an internal clocked element to an output pin

  - (or the degenerate path from an input pin to an output pin passing through no clocked logic)

 

The timing on paths is determined by static timing analysis. With the current tools (and for that matter all tools that I know about in both the FPGA and ASIC world), static timing analysis is performed on a single device only. It is not possible to do static timing analysis of a system that comprises two FPGAs.

 

Given this, your question:

 

My question is that , if two FPGAs are connected via SERDES modules, will the critical path calculation  include the I/OSERDES module delays as well other than the I/O pin delays and trace delays ?

 

is somewhat confusing.

 

If you are asking if there might be a system critical path from the OSERDES in one FPGA through an OBUF a board trace, an IBUF in another FPGA and to an ISERDES in another FPGA, the answer is yes; I/O timing can be among the most critical in a system.

 

However, there is no tool that can analyze this path for you automatically (or completely). Static timing analysis (STA) is performed on each FPGA independently. It is your responsibility as a designer to constrain the I/O interfaces of each FPGA when you are doing STA.

 

In general the timing constraints for an interface pin is derived from the characteristics of the system; the device driving/being driven by the FPGA pin and the trace delays between them. While there is some complexity to this (translating datasheet timing numbers and trace delays into set_input_delay and set_output_delay commands) for a system between an FPGA and an off-the-shelf device, this can be done (since the off-the-shelf device has either fixed behavior or a small number of programmable behaviors when it comes to timing). When the "other" device is also an FPGA, you have more degrees of freedom; you have to constrain both devices in a manner that is consistent with each other (so that they both represent the same behavior in the system), and get them both to pass. Pretty much nothing about this process is "automatic" - it is all up to you, the designer...

 

Avrum

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Guide
Guide
5,860 Views
Registered: ‎01-23-2009

When one talks about "critical path", one is talking about a static timing path that comes closest to violating (or violates by the most) the static timing requirement of the path.

 

In a single FPGA, the critical path may be internal (from a clocked resource inside the FPGA to another clocked resource inside the FPGA), or partly external;

  - an input path; from an input pin to an internal clocked element

  - an output path; from an internal clocked element to an output pin

  - (or the degenerate path from an input pin to an output pin passing through no clocked logic)

 

The timing on paths is determined by static timing analysis. With the current tools (and for that matter all tools that I know about in both the FPGA and ASIC world), static timing analysis is performed on a single device only. It is not possible to do static timing analysis of a system that comprises two FPGAs.

 

Given this, your question:

 

My question is that , if two FPGAs are connected via SERDES modules, will the critical path calculation  include the I/OSERDES module delays as well other than the I/O pin delays and trace delays ?

 

is somewhat confusing.

 

If you are asking if there might be a system critical path from the OSERDES in one FPGA through an OBUF a board trace, an IBUF in another FPGA and to an ISERDES in another FPGA, the answer is yes; I/O timing can be among the most critical in a system.

 

However, there is no tool that can analyze this path for you automatically (or completely). Static timing analysis (STA) is performed on each FPGA independently. It is your responsibility as a designer to constrain the I/O interfaces of each FPGA when you are doing STA.

 

In general the timing constraints for an interface pin is derived from the characteristics of the system; the device driving/being driven by the FPGA pin and the trace delays between them. While there is some complexity to this (translating datasheet timing numbers and trace delays into set_input_delay and set_output_delay commands) for a system between an FPGA and an off-the-shelf device, this can be done (since the off-the-shelf device has either fixed behavior or a small number of programmable behaviors when it comes to timing). When the "other" device is also an FPGA, you have more degrees of freedom; you have to constrain both devices in a manner that is consistent with each other (so that they both represent the same behavior in the system), and get them both to pass. Pretty much nothing about this process is "automatic" - it is all up to you, the designer...

 

Avrum

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Visitor
Visitor
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Registered: ‎08-10-2016

Thanks for the detailed explanation.

You are right that none of the tools these days are capable of handling multi-FPGA scenarios. But recently I came across this tool called Certify by Synopsys that claims of performing automatic timing analysis across multi-FPGA systems and produce very accurate static timing analysis estimates with post-route delay back annotation. Do you think its just a marketing stunt or is there any reality to it ? I have not used the tool myself and I am trying to find an easier way to do STA for mutli-FPGA systems.

 

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Xilinx Employee
Xilinx Employee
3,273 Views
Registered: ‎05-14-2008

For two given post-route results and the delay specification on board, it is possible to perform accurate STA. Because all at settled down, you have the max and min clock-to-out of the first FPGA and you have the setup/hold requirement of the second FPGA. Combined with the trace delay on board and clocks relationship, you can have an accurate STA.

 

Thanks

Vivian

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