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Observer
Observer
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Registered: ‎04-04-2008

Critical warning clock tree redefinition

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Hello,

I have a design inside a Pynq Z2 board with the ARM processor and some ADC and DAC controllers.

The controllers works with a 15Mhz clock derived from the ARM clock using the clock wizard.

When I route the design I have this critical warnings and the timing fails.

TIMING #1 Critical Warning Invalid clock redefinition on a clock tree. The primary clock design_1_i/clk_wiz_0/inst/clk_in1 is defined downstream of clock clk_fpga_0 and overrides its insertion delay and/or waveform definition

TIMING #1 Critical Warning The clocks clk_fpga_0 and clk_out1_design_1_clk_wiz_0_2 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_out1_design_1_clk_wiz_0_2]

TIMING #1 Critical Warning The clocks clk_fpga_0 and clk_out1_design_1_clk_wiz_0_2 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_out1_design_1_clk_wiz_0_2]

TIMING #1 Critical Warning A primary clock design_1_i/clk_wiz_0/inst/clk_in1 is created on an inappropriate internal pin design_1_i/clk_wiz_0/inst/clk_in1. It is not recommended to create a primary clock on a hierarchical pin when its driver pin has a fanout connected to multiple clock pins

I am stucked with it. 

Thank you

diagram.jpg

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Moderator
Moderator
171 Views
Registered: ‎11-04-2010

Re: Critical warning clock tree redefinition

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Hi, @meleth ,

Generally the prime clock should be created on the FPGA ports directly.

In the original design, the constraints in PLL/MMCM seem to take effect and create prime clock on input pin of PLL/MMCM, which is internal pin. The new created clock conflicts with the top level clocks.

To disable the create_clock constraints in PLL/MMCM can also resolve the issue.

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Observer
Observer
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Registered: ‎04-04-2008

Re: Critical warning clock tree redefinition

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Hi,

I removed the clock generator and reconfigure the PL clock from the Zynq to 15Mhz, and all the errors disappeared.

However, if anyone can point me what I've been doing wrong it would be really helpful for learning. Maybe any miss constraint?

Regards

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Highlighted
Moderator
Moderator
172 Views
Registered: ‎11-04-2010

Re: Critical warning clock tree redefinition

Jump to solution

Hi, @meleth ,

Generally the prime clock should be created on the FPGA ports directly.

In the original design, the constraints in PLL/MMCM seem to take effect and create prime clock on input pin of PLL/MMCM, which is internal pin. The new created clock conflicts with the top level clocks.

To disable the create_clock constraints in PLL/MMCM can also resolve the issue.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post