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patilvinayak5653
Observer
Observer
6,537 Views
Registered: ‎01-16-2013

DCM bounds frequency to 150.015MHz

In dff code I have used DCM from Language template.

 

------------------------------------------------------------------------------------------------------

module dff_async_reset (data,clk,reset,q);
input data, clk, reset ;
output q;
reg q;

DCM_BASE DCM_BASE_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLKFB(CLK1), // DCM clock feedback
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.RST(0) // DCM asynchronous reset input
);

BUFG BUFG_inst (
.O(CLK1), // Clock buffer output
.I(CLK0) // Clock buffer input
);


always @ ( posedge CLK1 or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

endmodule

-----------------------------------------------------------------------------------------------------------------

 

and then I have given constraint  like

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 3 ns HIGH 50%;
OFFSET = IN 3 ns VALID 3 ns BEFORE "clk" RISING;
OFFSET = OUT 3 ns AFTER "clk";

 

But timing constraint fails. I have attached timing constraint report image.

Report is saying that best case achievable for clock period is 6.66ns.

Whenever I am using DCM for any design it says   that best case achievable for clock period is 6.66ns.

 

 

Why it is happening ? Is it case that DCM can achieve maximum of 150 mhz?

 

 

 

I am working on vertex5. xilinx 13.2

 

 

timing constraint report.png
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2 Replies
austin
Scholar
Scholar
6,520 Views
Registered: ‎02-27-2008

p,

 

The DCM in V5 will run up to the max frequency of the global clock resources, 3ns, or 333 MHz is just fine (no problem).

 

I suspect you just can not run that fast because you have too much logic in your critical paths.

 

Try pipelining.  When a design does not meet timing, do not blame the DCM!

Austin Lesea
Principal Engineer
Xilinx San Jose
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hgleamon1
Teacher
Teacher
6,506 Views
Registered: ‎11-14-2011

Your failing path is the input clock to the design, rather than the DCM produced clock.

 

What other logic is being used by your "clk"?

 

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"That which we must learn to do, we learn by doing." - Aristotle
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