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conanandai100
Explorer
Explorer
11,202 Views
Registered: ‎12-01-2010

DDR data problem

Hi, all.

I find it is hard to deal with the DDR data sent by memory because of the special timing as follow.

1.jpg

The data and the clock arrive at the same time, which means there is no enough setup time for the data. I try to delay the clock, but new problem comes. When I run the place & route, the timing contraints fails. Because I use both the rising and falling edge of dqs to get the data. Now I really have no idea how to solve it. Is there a possible solution?

Thanks in advance.

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8 Replies
athandr
Xilinx Employee
Xilinx Employee
11,187 Views
Registered: ‎07-31-2012

Hi,

 

I observed that you posted your query under General Technical Discussions board. Since this is an timing query, I have now moved this to the Timing Analysis Board under Design Tools.

 

Please note that you have to post your queries under the correct Board in Forums to get a quicker response. The experts in a particular board might look at posts only in the particular board and hence you might miss out on some replies and your replies might get delayed. You can find the different board topics from the link - Forum Home Page.

 


Thanks,

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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bassman59
Historian
Historian
11,176 Views
Registered: ‎02-25-2008


@conanandai100 wrote:

Hi, all.

I find it is hard to deal with the DDR data sent by memory because of the special timing as follow.

1.jpg

The data and the clock arrive at the same time, which means there is no enough setup time for the data. I try to delay the clock, but new problem comes. When I run the place & route, the timing contraints fails. Because I use both the rising and falling edge of dqs to get the data. Now I really have no idea how to solve it. Is there a possible solution?

Thanks in advance.


Yes. You need to use proper OFFSET IN constraints and you might need to provide input delay on either the DQS or the DQ signals. The input delay ensures that you meet input setup and hold times. You can find a lot of discussion about this here. 

----------------------------Yes, I do this for a living.
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conanandai100
Explorer
Explorer
11,168 Views
Registered: ‎12-01-2010

Thank you. I see. Next time I will post my question in the right board.

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conanandai100
Explorer
Explorer
11,166 Views
Registered: ‎12-01-2010

Hi, Thanks for your reply.

Even if the setup time and hold time meet, the last data is still not available to me as there is no corresponding clock. And the dqs will keep low. Thus, I get no idea how to save the data into a memory. 

I am thinking I can read the MIG and see how it works with the DDR3 DQ and DQS signals. In the MIG core, ISERDES is used to deal with the DDR data. Is that the most common way as a DDR data solution? If so, I'd like to try.

Thanks again.

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avrumw
Expert
Expert
11,161 Views
Registered: ‎01-23-2009

Capturing data returning from a DDRx-SDRAM is probably one of the most complicated parts of the interface (in terms of timing). In the 7 series FPGAs Xilinx has even added special hard logic to deal with this (the Phaser).

 

As you showed in your picture, the returning data is edge aligned with the DQS. What this means is that if you are going to use the DQS to "capture" the DQ, then you need to delay the DQS by (approximately) 1/4 clock period (maybe with an IDELAY?) to put the DQS in the middle of the DQ. Then you can sample the DQ.

 

However, in FPGA, this can be somewhat complicated - now that you have clocked the data on the DQS, what do you do with it. The DQS isn't a free running clock, so you can't use it for logic so you have to transfer the data to some real clock - but what clock? Most FPGA based approaches don't actually clock the data using the DQS, but actually use a free running clock with some dynamic calibration to phase match to the DQS in order to sample the DQ...

 

The design of the PHY is difficult. That's why Xilinx has the MIG and in later architectures even has the dedicated hardware. Why are you trying to re-invent the wheel?

 

Avrum

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conanandai100
Explorer
Explorer
11,156 Views
Registered: ‎12-01-2010

Thank you so much for your helpful and quick reply.

 

The most annoying problem is that I don't know when the QDS comes. The NAND flash memory offers the DQS and DQ in a uncertain time. It's up to 20 ns. But may comes sooner. Thus, even if I get the data by both rising edge and falling edge of the DQS, I've no idea how to save it into BRAM or something else. As you say:


However, in FPGA, this can be somewhat complicated - now that you have clocked the data on the DQS, what do you do with it. The DQS isn't a free running clock, so you can't use it for logic so you have to transfer the data to some real clock - but what clock? Most FPGA based approaches don't actually clock the data using the DQS, but actually use a free running clock with some dynamic calibration to phase match to the DQS in order to sample the DQ...


Yes, I know I cannot use the DQS as a logic clock. Since the DQS is 100 MHz and my system clock is 200 MHz, I work for a month trying to calibrate the phase. Yet, no solution is found.

A free running clock and a DQS without fixed phase... I am trapped. Is there an IP core or a hardware device that can correspond these two clock?

 

 


Capturing data returning from a DDRx-SDRAM is probably one of the most complicated parts of the interface (in terms of timing). In the 7 series FPGAs Xilinx has even added special hard logic to deal with this (the Phaser).


 

I read the MIG code. Indeed, it's quite complicated and calls for a lot of logic resource. I think that's not my deal.

 

 

Anyway, thanks again for your reply.

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conanandai100
Explorer
Explorer
11,154 Views
Registered: ‎12-01-2010

Here is part of my original code. I found that the last the last couple of data were not saved into the register "rdreg". Though the rdreg1 and rdreg2 really got them. This is because after taking samples, I still needed a rising edge of DQS to trigger the process to save the last 16-bit data.

 

I've tried to trigger it manually. But the waveform of P&R simulation seemed to be not that nice.

 

1.jpg

2.jpg

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cbemlahe
Explorer
Explorer
1,071 Views
Registered: ‎09-18-2007

Did you ever find a solution to this? I too am looking to capture NAND data with DQS and wondering how to go about it.

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