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Contributor
Contributor
269 Views
Registered: ‎05-03-2014

DNA_PORT Clock Timing Problem: Spartan 6 ISE 14.7

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I coded up the DNA_PORT module to get a unique ID.

The problem is, the DNA_PORT needs a very low clock frequency of 2MHz max.     However, this is too low for the clock generators or PLLs to generate.    I can manually code up flip-flops to divide down the clock.    BUT, that loses the automatic timing checks.   How do I generate this the low DNA_PORT clock frequency while keeping the tool timing checks?

 

 

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Moderator
Moderator
239 Views
Registered: ‎11-04-2010

Re: DNA_PORT Clock Timing Problem: Spartan 6 ISE 14.7

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You can set period constraint on the output pin of the generated clock, then this clock will be analyzed. 

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Moderator
Moderator
240 Views
Registered: ‎11-04-2010

Re: DNA_PORT Clock Timing Problem: Spartan 6 ISE 14.7

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You can set period constraint on the output pin of the generated clock, then this clock will be analyzed. 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Contributor
Contributor
223 Views
Registered: ‎05-03-2014

Re: DNA_PORT Clock Timing Problem: Spartan 6 ISE 14.7

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Thank you.

This works partially.   I put in my vhdl code the following:

constant dna_clock_period : integer := CLOCK_PERIOD * 16;
constant dna_clock_period_str: string := integer'image(dna_clock_period);
attribute period: string;
attribute period of dna_clock : signal is dna_clock_period_str & "ns";

So the synthesizer picks this up is seen from the wrapper report:

Set property "PERIOD = 640NS" for signal <dna_clock>.

BUT, this does not get propagated into the main post-par timing report (.twr).   The slow clock is not seen as a derived clock in the .twr file.    BTW, setup failures will never be seen at these slow clock frequencies, but hold failures can happen at any frequency.

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Moderator
Moderator
221 Views
Registered: ‎11-04-2010

Re: DNA_PORT Clock Timing Problem: Spartan 6 ISE 14.7

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Please try to set the period constraint in UCF, instead of VHDL code.

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Don't forget to reply, kudo, and accept as solution.
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