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238 Views
Registered: ‎08-07-2018

[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

Hi,

We have done block design for enabling PL side ethernets using TEMAC IP.

Synthesis was successfully completed. While running implementation , I'm getting the following error.

[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'design_1_i/axi_ethernet_0/U0/mac/U0/tri_mode_ethernet_mac_idelayctrl_common_i' and 'design_1_i/axi_ethernet_1/U0/mac/U0/tri_mode_ethernet_mac_idelayctrl_common_i' have same IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp' but their RST signals are different

KIndly help us solving the error.

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5 Replies
Moderator
Moderator
231 Views
Registered: ‎11-04-2010

Re: [DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

Have you read AR-64542?

https://www.xilinx.com/support/answers/64542.html

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214 Views
Registered: ‎08-07-2018

Re: [DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

Hi,

We are not using the IP SelectIO Wizard IP.

We have used 2 nos of AXI 1G/2.5G ETHERNET SUB-SYSTEM to integrate with our design.

We are using XC7Z045.

Regards

Sangeetha

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Xilinx Employee
Xilinx Employee
206 Views
Registered: ‎02-27-2019

Re: [DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

Hi sangeethars@bel ,

Although you don't use SelectIO Wizard IP , AXI 1G/2.5G ETHERNET SUB-SYSTEM IP also contains "select io".

As Hong posted , this AR is also suitable for you .

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Moderator
Moderator
186 Views
Registered: ‎11-04-2010

Re: [DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

Hi, sangeethars@bel ,

Please don't focus on the IP. 

The point of the AR is to show you the way to modify the IODELAY_GROUP property of the idelayctrl in your design.

In general, you can add one idelayctrl into one IODELAY_GROUP, and during placement, tool will replicate the idelayctrl for every clock region if necessary.

Please use the method in the AR to set proper IODELAY GROUP for the idelayctrl instantiated in the design (before place_design).

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Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎05-14-2008

Re: [DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells

I think the issue is with the IPs based on the idelayctrl cell names mentioned in the error message.

'design_1_i/axi_ethernet_0/U0/mac/U0/tri_mode_ethernet_mac_idelayctrl_common_i' and 'design_1_i/axi_ethernet_1/U0/mac/U0/tri_mode_ethernet_mac_idelayctrl_common_i' 

You're using two ETHERNET IP in your design and there is IDELAYCTRL with IODELAY_GROUP constraint in the ETHERNET IP. Your issue is exactly the one in AR#64542 that hong suggested.

Each Ethernet IP has a group of idelayctrl and idelay cells with the same IODELAY_GROUP name. Because the two IPs are the same one, the IODELAY_GROUP name used for the two groups is the same one which is not allowed. You need to change the IODELAY_GROUP name in one of the IPs to be a different one, using the method in AR#64542.

You can find the IP source files to be edited according to the cell name in the error message. The file is where the "tri_mode_ethernet_mac_idelayctrl_common_i" cell is instantiated.

-vivian

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