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legendbb
Voyager
Voyager
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Registered: ‎07-28-2008

DSP48 delay Tdspcko_M_B0REG (ISE) vs Prop_dsp48a1_CLK_M (planAhead)

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None of the above Symbols (Tdspcko_M_B0REG & Prop_dsp48a1_CLK_M) are listed in Spartan-6 FPGA Data Sheet: DC and Switching Characteristics (DS162).

 

I can assume its mean from schematics with reference of others from datasheet, it's Clock to Output delay from Input Register B0 to M Register.

 

But for my curiosity, are there a better source of documentation for these delay explanation?

 

The very origin of my concern and curiosity for these are the delay values are listed differently in ISE (3.804ns) & planAhead (4.695ns). Absolutely same device type, since the planAhead project was imported from the ISE project.

 

Please provide me some hints about the meaning of the "(r)" in planAhead timing report; I hope it's not "Roughly". I figured the mean of "e" in ISE years back myself; after failing in finding any official reference.

 

BTW, none of the hyperlinks work in my planAhead (linux) and I don't find where to configure HTML browser as in ISE.

 

Thanks in advanced for any comments,

 

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
legendbb
Voyager
Voyager
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Registered: ‎07-28-2008

Thanks for comments.

 

I guess the tool and technology are moving on fast pace, it's really challenging for documentation to catch up.

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