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Visitor xuser72
Visitor
221 Views
Registered: ‎10-10-2018

DVI Receiver Timing Constraint set_input_delay

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Hello Xilinx team, can you explain me how to calculate tco min and tco max for TFP401A-EP DVI Receiver for set_input_delay constraints.


I use it with 148.5MHz clk freq. and on a second Board with 74.25MHz clock from the Reveiver IC to my FPGA.
Can I use the setup and hold values of the datasheet directly or do I have to calculate the values which depends on the period time Tclk, rise and fall times of data and clock? 
I use it with 1pixel/clock on the rising edge. 

Clock 148.5MHz:
tco min = ?
tco max = ?

Clock 74.25MHz:
tco min = ?
tco max = ?

 

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3 Replies
Visitor xuser72
Visitor
82 Views
Registered: ‎10-10-2018

Re: DVI Receiver Timing Constraint set_input_delay

No Response?
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Xilinx Employee
Xilinx Employee
74 Views
Registered: ‎05-14-2008

Re: DVI Receiver Timing Constraint set_input_delay

Can you provide a diagram of the interface connections between the DVI Receiver and the FPGA?

What data is the FPGA receiving and which is the capturing clock on the FPGA side?

In general, you can first try to match the interface to one of the "input delay constraints template" in the Vivado language template.

And then you can use the data given in the device data sheet to calculate the parameters used in the input delay constraints in the template.

-vivian

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Visitor xuser72
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Registered: ‎10-10-2018

Re: DVI Receiver Timing Constraint set_input_delay

 
DVI_IN.jpg
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