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cheekerz
Visitor
Visitor
9,418 Views
Registered: ‎04-18-2015

Decreasing clock frequency increases negative slack

Hi,

 

When implementing my design I end up with both negative setup slack and hold slack. My first thought was to decrease the frequency of the clock and see if this resolved the issue. However, as the clock decreased the setup slack increased. I have tried various phys_opt options and run them with various clock speeds but no matter what i try the higher clock speeds get closer to 0 slack. Could there possibly by some other optimisations that are automatically enabled at higher frequencies that could be enabled with the lower frequencies in order to meet timing contraints?

 

The kind of difference in slack is as follows:

800MHz ~= -13ns

100MHz ~= -18ns

40MHz ~= -49ns

 

Any thoughts or advice would be greatly appreciated.

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6 Replies
austin
Scholar
Scholar
9,396 Views
Registered: ‎02-27-2008

ch,

 

Look at your constraints.  I suspect there is something wrong in how the design is being constrained.

 

Two digit ns numbers you have posted are unusual to say the least.  I would not draw any conclusions from them.

 

It looks like "garbage in:  garbage out."

Austin Lesea
Principal Engineer
Xilinx San Jose
austin
Scholar
Scholar
9,394 Views
Registered: ‎02-27-2008

Further,

 

I am reminded of what Peter Alfke would say:

 

"When your car stops running suddenly, do yopen the hood and start checking the engine, or do you look to see if you have run out of fuel?"

 

Do not become fixated on "the problem" until you know you are trying to fix the right issue.  Look at the easy items first (constraints are 99% of the problems).

Austin Lesea
Principal Engineer
Xilinx San Jose
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cheekerz
Visitor
Visitor
9,383 Views
Registered: ‎04-18-2015

Thanks for the reply, I am fairly new to FPGA use which is clearly showing. I wonder if you can see anything obviously wrong with the constraints I have setup:

 

I am using the Clocking Wizard IP to generate 3 clock signals for use in my design. The constraints I have are a generated one specifying the frequency and jitter of the input clock, however, this is not in my .xdc file but can be seen under 'Edit Timing Constraints'. I have a set of input and output pins that are constrained to LEDs and buttons on the board (Zedboard). Is there I am missing that would cause the timing contraints to fail?

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austin
Scholar
Scholar
9,355 Views
Registered: ‎02-27-2008

Which tools? (ISE or Vivado)

 

When you have three clocks, and you have paths that cxross from one to another, you are crossing clock domains.  At those points you need synchronizers.  The constarints get complex, as some paths get constrainede, and some paths do not.

 

Depending on the tool the philosophy is different (ISE assumes nothing crosses, and needs you to tell it what to do, Vivado assumes everything crosses, and you have to tell the tool to ignore paths that are not to be constrained across the domains (only constrained within one domain).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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muzaffer
Teacher
Teacher
9,041 Views
Registered: ‎03-31-2012

It seems like you have multiple clocks and the slower you make them the longer the separation is between the edges of different clocks which makes your timing worse. Are you using a single PLL to generate your 3 clocks? Also are you constraining only the input to the PLL or any of the outputs too. If you can show your timing report and the constraints we can make more educated guesses on what your problem is.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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yashp
Moderator
Moderator
9,039 Views
Registered: ‎01-16-2013

Hi,

Please share your timing report.
It will be easy to evaluate and provide the suggestions.

I am suspecting this issue is under CDC paths.

Thanks,
Yash
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