04-18-2015 06:19 PM
When implementing my design I end up with both negative setup slack and hold slack. My first thought was to decrease the frequency of the clock and see if this resolved the issue. However, as the clock decreased the setup slack increased. I have tried various phys_opt options and run them with various clock speeds but no matter what i try the higher clock speeds get closer to 0 slack. Could there possibly by some other optimisations that are automatically enabled at higher frequencies that could be enabled with the lower frequencies in order to meet timing contraints?
The kind of difference in slack is as follows:
800MHz ~= -13ns
100MHz ~= -18ns
40MHz ~= -49ns
Any thoughts or advice would be greatly appreciated.
04-19-2015 08:31 AM
Look at your constraints. I suspect there is something wrong in how the design is being constrained.
Two digit ns numbers you have posted are unusual to say the least. I would not draw any conclusions from them.
It looks like "garbage in: garbage out."
04-19-2015 08:35 AM
I am reminded of what Peter Alfke would say:
"When your car stops running suddenly, do yopen the hood and start checking the engine, or do you look to see if you have run out of fuel?"
Do not become fixated on "the problem" until you know you are trying to fix the right issue. Look at the easy items first (constraints are 99% of the problems).
04-19-2015 10:02 AM
Thanks for the reply, I am fairly new to FPGA use which is clearly showing. I wonder if you can see anything obviously wrong with the constraints I have setup:
I am using the Clocking Wizard IP to generate 3 clock signals for use in my design. The constraints I have are a generated one specifying the frequency and jitter of the input clock, however, this is not in my .xdc file but can be seen under 'Edit Timing Constraints'. I have a set of input and output pins that are constrained to LEDs and buttons on the board (Zedboard). Is there I am missing that would cause the timing contraints to fail?
04-20-2015 07:08 AM
Which tools? (ISE or Vivado)
When you have three clocks, and you have paths that cxross from one to another, you are crossing clock domains. At those points you need synchronizers. The constarints get complex, as some paths get constrainede, and some paths do not.
Depending on the tool the philosophy is different (ISE assumes nothing crosses, and needs you to tell it what to do, Vivado assumes everything crosses, and you have to tell the tool to ignore paths that are not to be constrained across the domains (only constrained within one domain).
05-16-2015 10:59 PM
05-17-2015 01:05 AM