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Voyager
Voyager
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Registered: ‎04-11-2016

Default Time scale in vivado simulator

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Hi,

I would like to know which time scale is in vivado simulator by default? ps or ns or us?

Does setting timescale in source code like `timescale 1ps/1ps have any impact on it?

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Guide
Guide
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Registered: ‎01-23-2009

The 'timescale specifies how time is managed in the Verilog simulator. It contains 2 numbers, the time unit and the precision; so 1ns/100ps means that the time unit for the Verilog code that follows has a time unit of 1ns with a resolution of 100ps. So this means that #1 means 1ns, #1.1 mean 1.1ns, but that #1.15 also means 1.1ns (since the resolution is only in increments of 100ps, or 0.1ns).

The resolution is a bit more complicated, because the resolution in a simulation is the value of the smallest resolution specified in any code. So if you have a 1ns/100ps in one part of the code and 1ns/1ps in another part of the code, the code is all effectively 1ns/1ps.

The 'timescale is a compiler directive, so it pertains to the code that is parsed after this code - it is not related to modules or even necessarily to files. It is therefore customary to either:

  • Put a 'timescale at the top of every file
  • Don't use it at all (in which case the simulator will use the default, which I think is 1ps/1ps
  • Put it only in the top of your testbench and ensure that it is the first file read

If you do not have a 'timescale in the first file/files read, but you do in a later file, you will get a warning message...

Avrum

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Teacher
Teacher
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Registered: ‎07-09-2009

Simulator is in ps,

in verilog, as far as I remember, the `timescale 1ps/1ps  only affects things like #10 assignment,

   where if you put `timescale 1ps/1ps  and have #10, thats 10 ps,

    where as if you put `timescale 100ps/100ps  and have #10, thats 1000 ps ( 1 ns )

 

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Highlighted
Guide
Guide
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Registered: ‎01-23-2009

The 'timescale specifies how time is managed in the Verilog simulator. It contains 2 numbers, the time unit and the precision; so 1ns/100ps means that the time unit for the Verilog code that follows has a time unit of 1ns with a resolution of 100ps. So this means that #1 means 1ns, #1.1 mean 1.1ns, but that #1.15 also means 1.1ns (since the resolution is only in increments of 100ps, or 0.1ns).

The resolution is a bit more complicated, because the resolution in a simulation is the value of the smallest resolution specified in any code. So if you have a 1ns/100ps in one part of the code and 1ns/1ps in another part of the code, the code is all effectively 1ns/1ps.

The 'timescale is a compiler directive, so it pertains to the code that is parsed after this code - it is not related to modules or even necessarily to files. It is therefore customary to either:

  • Put a 'timescale at the top of every file
  • Don't use it at all (in which case the simulator will use the default, which I think is 1ps/1ps
  • Put it only in the top of your testbench and ensure that it is the first file read

If you do not have a 'timescale in the first file/files read, but you do in a later file, you will get a warning message...

Avrum

View solution in original post

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Voyager
Voyager
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Registered: ‎04-11-2016

@avrumw 

Don't use it at all (in which case the simulator will use the default, which I think is 1ps/1ps      :)

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