11-13-2017 01:47 AM
I have modules in my source code which handle the SPI slave devices from FPGA. Basically the FPGA planned to operate at 100-200MHz and where as the SPI interface is planned to operate at 20MHz maximum. How to define timing constraints in this case?
According to the timing wizard, the output delays are mapped with the master clk input. So how to define the output delays for this? Let us assume master clock for FPGA 200MHz, SPI interface to ADC operates at 20MHz. And setup/home time for SCLK, SDATA is of 25 ns.
11-13-2017 01:57 AM - edited 11-13-2017 01:58 AM
Are you using a Xilinx SPI IP core? Then you are in luck.
Generate this IP and the timing constraints will be provided to you. You can study the xdc file and clear your doubts.
Even if you are not using a xilinx IP, still I can recommend you to generate the Xilinx SPI IP core and look inside the xdc file to get an idea as to how it is done.