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Visitor
Visitor
6,917 Views
Registered: ‎04-09-2010

Delay and Clock doubt

I'm getting the same time for delay and the clock period. Is it normal or does that mean there is something wrong with my design ?

 

Timing constraint: Default period analysis for Clock 'CLK'

  Clock period: 6.845ns (frequency: 146.092MHz)

  Total number of paths / destination ports: 249 / 31

-------------------------------------------------------------------------

Delay:               6.845ns (Levels of Logic = 10)

  Source:            count/O_sig_1 (FF)

  Destination:       **bleep**er/D_out_6 (FF)

  Source Clock:      CLK rising

  Destination Clock: CLK rising

 

  Data Path: count/O_sig_1 to **bleep**er/D_out_6

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     FDCE:C->Q             3   0.886   1.188  count/O_sig_1 (count/O_sig_1)

     LUT2:I0->O            9   0.418   1.935  AddS/RES_cmp_eq00002 (AddS/RES_cmp_eq0000)

     LUT3:I2->O            1   0.418   0.000  AddS/Maddsub_RES_lut<0> (N7)

     MUXCY:S->O            1   0.461   0.000  AddS/Maddsub_RES_cy<0> (AddS/Maddsub_RES_cy<0>)

     MUXCY:CI->O           1   0.052   0.000  AddS/Maddsub_RES_cy<1> (AddS/Maddsub_RES_cy<1>)

     MUXCY:CI->O           1   0.052   0.000  AddS/Maddsub_RES_cy<2> (AddS/Maddsub_RES_cy<2>)

     MUXCY:CI->O           1   0.052   0.000  AddS/Maddsub_RES_cy<3> (AddS/Maddsub_RES_cy<3>)

     MUXCY:CI->O           1   0.052   0.000  AddS/Maddsub_RES_cy<4> (AddS/Maddsub_RES_cy<4>)

     MUXCY:CI->O           1   0.052   0.000  AddS/Maddsub_RES_cy<5> (AddS/Maddsub_RES_cy<5>)

     MUXCY:CI->O           0   0.052   0.000  AddS/Maddsub_RES_cy<6> (AddS/Maddsub_RES_cy<6>)

     XORCY:CI->O           2   0.579   0.000  AddS/Maddsub_RES_xor<7> (Y_out_7_OBUF)

     FDC:D                     0.648          **bleep**er/D_out_6

    ----------------------------------------

    Total                      6.845ns (3.722ns logic, 3.123ns route)

                                       (54.4% logic, 45.6% route)

 

please help me to resolve my doubt

thanks 

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Historian
Historian
6,909 Views
Registered: ‎02-25-2008

Re: Delay and Clock doubt

Looks like you haven't specified a clock period constraint, so the tools tell you the best you can do is whatever turns out to be the slowest path.
----------------------------Yes, I do this for a living.
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Visitor
Visitor
6,906 Views
Registered: ‎04-09-2010

Re: Delay and Clock doubt

Hmm can you tell me how I can specify a clock period on ISE 9.2i? because yes I didnt follow such a step
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Historian
Historian
6,903 Views
Registered: ‎02-25-2008

Re: Delay and Clock doubt


vampiro wrote:
Hmm can you tell me how I can specify a clock period on ISE 9.2i? because yes I didnt follow such a step

Read the fine manual, called the "constraints guide."

----------------------------Yes, I do this for a living.
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Visitor
Visitor
6,900 Views
Registered: ‎04-09-2010

Re: Delay and Clock doubt

Thanks :)
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Teacher
Teacher
6,875 Views
Registered: ‎07-09-2009

Re: Delay and Clock doubt

Hi

 

 You might want to look at austins rather xcelent tutorial :

    it covers all you ask in easy pages.

 

 

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-4-of-5/ba-p/66696

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