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timo-ge
Explorer
Explorer
11,220 Views
Registered: ‎11-12-2007

Derived constraints on PERIOD and FROM-TO

Hi Guys,

I have read all the answer records, CGD, and topics in this forum and I still don't get it:

 

I get the translation warnings about:

ConstraintSystem:203 - TNM : CLK_xxx was distributed to a DCM but new TNM constraints were not derived. .... etc...

 

I am using a processor desing in XPS/EDK: (12.4) which is doing something like this:

clkinput -> clock_generator

clock_generator -> clk1

clk1 -> DCM -> clk2

 

contrain FROM-TO between clk1 and clk2

and I get the above warning. How is this done properly. The answer record says to specify an additional TNM_NET which I did:

NET clk_in TNM_NET = clk_in;
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 10000 ps;

 

NET clk1 TNM_NET = FFS clk1_grp; ## 100MHz
NET clk2 TNM_NET = FFS clk2_grp; ## 25MHz

TIMESPEC TS_ASYNC1 = FROM clk1 TO clk2 TIG; 

 

What is going wrong here? I know the tools will generate automatically derived constraints for all clocks going through the cock_generator or DCM, but how to handle this to avoid this warning.

 

Thanks,

timo-ge

 

 

 

 

 

 

 

 

 

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5 Replies
austin
Scholar
Scholar
11,210 Views
Registered: ‎02-27-2008

t,

 

The DCM removes delay, so the outputs are all phase aligned with the CLKFB.  So, a constarint across a DCM is meaningless (doesn't do anything, because it can not).

 

What is "clock generator" in you post?  Is in another DCM, using its CLKFX output?  If so, cascaded DCMs can be a problem, due to increased jitter.  Reagrdless, a new period constraint on a the new clock is required.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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timo-ge
Explorer
Explorer
11,192 Views
Registered: ‎11-12-2007

I'm sorry, maybe I was a little bit unspecific, this was a bad example. 

I am using clock_generator_4_01_a from EDK. I am using all 8 clock outputs to clock an complex system in Virtex5 with PPC440, DDR2, PLB, OPB, etc...

I know, there will be auto-generated constraints for the PLL and DCMs inside the clock_generator,

Now I need to constrain false-paths an multi-cycle paths in some of the pcores I am using.  I get the above warning message, which I learned is not good, becuase the PERIOD constraint will not propagate through if using a FROM-TO on the same net. 

 

How do I get rid of this warning? 

 

Thanks for the help. 

 

timo.

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mrbietola
Scholar
Scholar
11,157 Views
Registered: ‎05-31-2012

Same problem with clock generator in XPS too.

I have an other issue too.

I have 2 clock generator, the first have as clkin a differential 100MHz clk.

I tried to connect this clock to the 2° clock generator clock in, but it fails map because the MMCM used in the clock generator 2° is not in the same region as the differential clk pin.

 

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vemulad
Xilinx Employee
Xilinx Employee
11,138 Views
Registered: ‎09-20-2012

Hi,

 

What is the device you were targetting?

 

The error could be due to limitation of the device. You can find the details about the restrictions of MMCM/IOB placement in the device clocking resources user guide.

 

As the error message says try locking both of the MMCM to the same clock region as that of IOB.

 

Thanks,

Deepika.

Thanks,
Deepika.
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mrbietola
Scholar
Scholar
11,131 Views
Registered: ‎05-31-2012

it's a Kintex 7, i will try

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