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Visitor chups
Visitor
4,061 Views
Registered: ‎03-03-2017

Design failed due to WNS and TNS timing violations

Hi all,

I'm working with a NexysVideo board and using Vivado to implement my design. The systhsis works well, but the implementation has some warnings of THS and WHS. 

timesummary.png

For information, I used the following configuration to create a DLL:

clockconfiguration.png

I post the vhdl code and the time report in attachments. 

I'm a newbie  in FPGA and I had already used this configuration in an older version of my project, it worked without timing violations, I cannot understand why they appear. Could you please tell me how the violations occur and suggest any solutions?

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6 Replies
Xilinx Employee
Xilinx Employee
4,047 Views
Registered: ‎01-05-2017

Re: Design failed due to WNS and TNS timing violations

Hi,

 

What version of Vivado are you using and can you upload the constraints that you used?

 

Best Regards,

David

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Voyager
Voyager
4,044 Views
Registered: ‎06-24-2013

Re: Design failed due to WNS and TNS timing violations

@chups

 

The PLL is fine and unlikely to cause any issues.

 

You might want to inspect the pathes failing the timing though.

 

If you can upload the project, I can take a look ...

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Guide avrumw
Guide
4,037 Views
Registered: ‎01-23-2009

Re: Design failed due to WNS and TNS timing violations

The "time_report.txt" and the design summary page you are showing are clearly not from the same design.

 

The time_report.txt has no violations and a tiny number of endpoints (1303), whereas the summary you are showing has massive violations and a much larger number of endpoints (92187).

 

The answer to why you are getting these failures will be found in the timing summary report, but the file you sent us is clearly not the right one.

 

Avrum

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Visitor chups
Visitor
3,928 Views
Registered: ‎03-03-2017

Re: Design failed due to WNS and TNS timing violations

@avrumw

I modified the code and re-implement the program, here is the new timing report, could you take a look please?time report.png

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Voyager
Voyager
3,918 Views
Registered: ‎06-24-2013

Re: Design failed due to WNS and TNS timing violations

Hey @chups,

 

It looks like you have quite long logic pathes in your design.

You might consider adding one or the other register to those pathes if pipelining is an option.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Guide avrumw
Guide
3,907 Views
Registered: ‎01-23-2009

Re: Design failed due to WNS and TNS timing violations

In a nutshell, your design is not architected to operate at this frequency.

 

The failing path has 5 LUTs and 9 CARRY elements in at least 3 separate chains. This is probably too much. The design needs to be re-architected to do more pipelining (or completely change how the work is done).

 

We have no idea what this design does, nor how it is architected, and we have limited information from the timing summary, but it looks like you have an immense array of flip-flops - the Array_out_reg appears to have at least 2203x13 elements - this is an array of 28,639 flip-flops, which is absolutely huge - this one array is around 10% of the total number of flip-flops in the FPGA (assuming it is not larger than what I have found, which is certainly possible). Without knowing more about the application, we can't tell if this is a reasonable approach, but it certainly looks suspicious. Usually, this amount of storage is designed to be placed in a block RAM. However, using a block RAM has restrictions - you have to make sure your access pattern conforms to this - no more than two operations on the array per clock (where each operation is a read or a write, or, in some modes and if they are to the same address a read and write at the same time).

 

Avrum

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