02-21-2017 04:09 PM
I have a pretty big design with DDR ram, DSP and some IO interface. It has many clock domain so I used set_clock_groups -asynchronous to ignore timing between clocks as all my cross clock signals are not fast-changing. As my design gets bigger and bigger, my DDR MIG failed to work after I add a module with cross clock signals. The module doesn't use any inputs or output signals from the MIG. Since the MIG is from Xilinx, I can only do so little with it. Looking for suggestion on what I can do about this problem.
Thanks for helping,
02-21-2017 09:55 PM
Which FPGA device and memory part are you using?
Do you see calibration failure in MIG after design change?
02-22-2017 08:01 AM
I am using EVAL board VC707 with the memory part that it come with.I will look to see if it fails calibration. If it fails calibration, what does it really mean?
03-06-2017 08:48 PM - edited 03-06-2017 08:50 PM
Check this AR https://www.xilinx.com/support/answers/51954.html
Generate the MIG design by following the steps in XTP206 https://www.xilinx.com/member/forms/download/design-license.html?cid=389659&filename=xtp206-vc707-mig-c-2015-1.pdf
You can also download the bit/ltx files located in ready_for_download folder in XTP design files from https://www.xilinx.com/member/forms/download/design-license.html?cid=389667&filename=rdf0196-vc707-mig-c-2015-1.zip