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Visitor
Visitor
2,722 Views
Registered: ‎06-20-2014

Design meets timing but DDR ram failed to work after adding non-related module with cross clocking signals

I have a pretty big design with DDR ram, DSP and some IO interface. It has many clock domain so I used set_clock_groups -asynchronous to ignore timing between clocks as all my cross clock signals are not fast-changing. As my design gets bigger and bigger, my DDR MIG failed to work after I add a module with cross clock signals. The module doesn't use any inputs or output signals from the MIG. Since the MIG is from Xilinx, I can only do so little with it. Looking for suggestion on what I can do about this problem.

 

Thanks for helping,

Victor

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Xilinx Employee
Xilinx Employee
2,685 Views
Registered: ‎09-20-2012

Hi @leongnrl

 

Which FPGA device and memory part are you using?

 

Do you see calibration failure in MIG after design change?

Thanks,
Deepika.
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Visitor
Visitor
2,670 Views
Registered: ‎06-20-2014

I am using EVAL board VC707 with the memory part that it come with.I will look to see if it fails calibration. If it fails calibration, what does it really mean?

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Xilinx Employee
Xilinx Employee
2,519 Views
Registered: ‎09-20-2012

Hi @leongnrl

 

Check this AR https://www.xilinx.com/support/answers/51954.html

 

Generate the MIG design by following the steps in XTP206 https://www.xilinx.com/member/forms/download/design-license.html?cid=389659&filename=xtp206-vc707-mig-c-2015-1.pdf

 

You can also download the bit/ltx files located in ready_for_download folder in XTP design files from https://www.xilinx.com/member/forms/download/design-license.html?cid=389667&filename=rdf0196-vc707-mig-c-2015-1.zip

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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