cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
32,097 Views
Registered: ‎10-30-2008

Difference between IBUFG and BUFG clock

Hi all. I have implement a module in ISE with two clock inputs. One is 100M Hz and the other is 70M Hz. I set the timing constraint to 105M Hz and 73M Hz. There is no timing error during the implement.

 

Now when I try to creat a wrap of this module, which include DCM with BUFG (generate 100M Hz SRAM clock from 100M input clock) and PLL with BUFG (generate 70M Hz from 100M input clock). I set the timing constraint to 100M Hz for the input clock. When I run implement, the result is shocked. The timing report indicates that my module is only able to run at 16M Hz. I read the report and find that the clock skew is 3 ns.

 

I support there might be some difference between the IBUFG and BUFG. Could anyone please give me some advices?

 

Many thanks. 

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
32,078 Views
Registered: ‎11-28-2007

For the design with DCM/PLL, is the clock skew reported between the 100MHz and 70MHz clocks?

 

Cheers,

Jim

 

PS. IBUFG and BUFG are totally different things, but I must admit the names are confusing.

Cheers,
Jim
0 Kudos
Observer
Observer
32,046 Views
Registered: ‎10-30-2008

Thanks for your reply. The clock skew is between the 100MHz and 70MHz. I have modified my module by reducing the 70MHz. There is no timing error. However, could you please give me some suggestions if I don't reduce the 70MHz?

 

Many thanks. 

0 Kudos
Highlighted
Voyager
Voyager
31,998 Views
Registered: ‎08-30-2007

 

An IBUFG drives a global clock net from an external pin.

 

A BUFG drives a global clock net from an internal signal.

 

As to your timing problem, I don't think you've given us quite enough data.

 

I don't know how you have things connected or which part you're using,

but you should be able to use a DCM to buffer the 100 MHz clock AND

create a 70 MHz clock.

 

Maybe you should post your clock logic and your constraints file.

 

John Providenza