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Participant mwerner2000
Participant
4,167 Views
Registered: ‎06-05-2015

Difference in delay values when analyzing Setup and Hold

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Dear Ladies and Gentlemen,

 

I have a question about the Vivado timing analyzer. Why are there differences in the delay (propagation delays) shown in the timing analyzer for the very same component when looking at Setup and Hold analysis? I added the specific reports. Let me give you an example from the reports:

 

IBUF (SITE E1) delay for SETUP is 0.397 ns

IBUF (SITE E1) delay for HOLD is 0.846 ns

 

Same goes for the IDELAYE2:

 

IDLEAYE2 (IDELAY_X1Y74) delay for SETUP is 1.338 ns

IDLEAYE2 (IDELAY_X1Y74) delay for HOLD is 2.263 ns

 

I was expecting these values to be the same.

I am obviously missing something here. Can someone please explain the difference?

 

Thank you very much in advance.

 

Sincerely,

Martin Werner

Setup.png
Hold.png
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1 Solution

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Xilinx Employee
Xilinx Employee
7,830 Views
Registered: ‎02-14-2014

Re: Difference in delay values when analyzing Setup and Hold

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Hello @mwerner2000,

 

Below threads can help you to know reason behind this difference

https://forums.xilinx.com/t5/Timing-Analysis/Why-does-the-delay-differs-in-setup-and-hold-analysis/td-p/401271

https://forums.xilinx.com/t5/General-Technical-Discussion/What-is-the-mean-of-process-corner/td-p/326871

Regards,
Ashish
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5 Replies
Xilinx Employee
Xilinx Employee
7,831 Views
Registered: ‎02-14-2014

Re: Difference in delay values when analyzing Setup and Hold

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Hello @mwerner2000,

 

Below threads can help you to know reason behind this difference

https://forums.xilinx.com/t5/Timing-Analysis/Why-does-the-delay-differs-in-setup-and-hold-analysis/td-p/401271

https://forums.xilinx.com/t5/General-Technical-Discussion/What-is-the-mean-of-process-corner/td-p/326871

Regards,
Ashish
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Moderator
Moderator
4,155 Views
Registered: ‎01-16-2013

Re: Difference in delay values when analyzing Setup and Hold

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Hi,

This is expected because tool analyze the paths in four different process corners and consider the worst case for setup and hold and report it.

If you see setup (max at fast process corner) at the same time hold (min at slow process corner). Tool consider Max-Max, Max-min, Min-Max amd Min-Min value for analysis and provide the work case.

If report shows it's passing for worst case it will definitely pass for other cases.

Thanks,
Yash
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Participant mwerner2000
Participant
4,154 Views
Registered: ‎06-05-2015

Re: Difference in delay values when analyzing Setup and Hold

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Dear Ashishd,

 

ah yes ofc the process corners. Thank you. I somehow overlooked it in the report.

 

Sincerely,

Martin Werner

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Visitor pma-mt
Visitor
3,904 Views
Registered: ‎12-12-2016

Re: Difference in delay values when analyzing Setup and Hold

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Hi,

 

I would like to ask one question related to these delays in the first post:

 

IDLEAYE2 (IDELAY_X1Y74) delay for SETUP is 1.338 ns

IDLEAYE2 (IDELAY_X1Y74) delay for HOLD is 2.263 ns

Documentation says that IDELAYs are continuously calibrated (when IDELAYCTRL is properly used). Are these numbers actually telling me that the calibration mechanism has limitations and my design should be able to handle that much variation in IDELAY propagation times?

 

Regards,

Petteri

Regards,
Petteri
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Historian
Historian
3,897 Views
Registered: ‎01-23-2009

Re: Difference in delay values when analyzing Setup and Hold

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Tool consider Max-Max, Max-min, Min-Max amd Min-Min value for analysis and provide the work case.

 

Careful with the terminology here...

 

All timing checks (setup and hold) are done at two process corners - slow and fast.

 

When doing a setup check, the maximum delay on elements at that corner are use for the source clock delay (SCD) and datapath delay (DP), whereas the minimum delay on elements are used at that corner for the destination clock delay (DCD). Therefore, for a setup check at the slow process corner, the "SLOW_MAX" delay numbers are used for the SCD and DP, whereas the "SLOW_MIN" is used for the DCD.

 

For a hold check it is the other way around - the minimum delay is used for SCD and DP, whereas the maximum is used for DCD; so for a hold at slow process corner, it would use SLOW_MIN for SCD and DP, and SLOW_MAX for DCD.

 

The same is true at the fast corner:

  - for setup it uses FAST_MAX for SCD and DP, and FAST_MIN for DCD

  - for hold it uses FAST_MIN for SCD and DP, and FAST_MAX for DCD

 

I point this out since this is critical to understanding timing reports from Vivado.

 

Also, I want to specifically point out that Vivado does not mix slow and fast timing corners in the same analysis (i.e. SLOW for some parts of the path and FAST for the others) - the text above might be interpreted to imply that it does.

 

Avrum

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