01-16-2014 02:17 PM
I'm supporting a design that has two different serial interfaces that share the same clock (CLK), data in (DIN), and data out (DOUT) pins. Here are some of the design requirements and characteristics.
1. Interface #1 (IF1) is SPI-ish and doesn't use any edges of the DIN line.
2. Interface #2 (IF2) has both SPI and I2C characteristics. Both DIN rising and falling edges are used to sample the CLK line for start/stop framing. This implies that there are timing constraints for this interface where both pins act as clocks.
3. Both of the interfaces must be available at run-time, but only one of the interfaces can be enabled at a time. This selection is made at run-time by writing to a configuration register.
4. Only the enabled serial interface drives the DOUT pin but the CLK and DIN pins are connected to both serial serial interface blocks.
5. The clocks are not free-running.
6. IF1 (SPI-ish) runs at 25 MHz while the IF2 (SPI/I2C hybrid) runs at 10 MHz.
The problem is how to write constraints that will apply to each interface separately when both interfaces share the same clock pin. A brute force approach is to apply the higher clock speed constraints of IF1 to the IF2 interface that uses both CLK and DIN edges. But the IF2 CLK and DIN edges are offset by 1/4 clock cycle, so applying the IF1 clock frequency to the IF2 interface results in overly restrictive constraints and a corresponding failure to close timing.
This is an emulation of an ASIC, so timing that is difficult for the FPGA to meet is not an issue for the ASIC. The emulation target chip is a Virtex-6 LX240.
There is no concern if valid timing at IF1 when it is selected violates the timing of unselected IF2, and vice versa, as the the unselected interface is a don't care at that point.
How can I specifiy completely different timing for IF1 and IF2 when they share the same CLK and DIN pins?
01-16-2014 07:22 PM
When you say you have problems meeting the tighter timing constraints, are you talking about the interface pin setup/hold timing or do you mean the clock period on the internal logic?
Internal period constraints are fairly easy to override with from : to constraints. The general idea is to set the period to the more restrictive value, 40 ns in your case. Then form a time group for the registers in the design that only implement the 10 Mhz interface and make a constraint from that timing group to itself at 100 ns. If you use both clock edges you may need to have multiple constraints for signals that pass from one edge to the other as well. Use the rising and falling keywords in the from : to constraints to limit the application to paths starting and ending on a particular edge.
As to the external pin constraints, I have to admit that I still don't quite grasp what you're trying to do with that. There may be some similar mechanism to ignore or relax setup constraints if you have more than one register that latches the same input signal.