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Contributor
Contributor
351 Views
Registered: ‎12-10-2018

Differential Clock Output

Hello everybody!

I have a design which I have to transmit a clock using an output pin. The output clock should be differential and I have used ODDR + OBUFDS to drive the output.

The problem is that when I program my board, sometimes I can't see the correct clocks on the board using the ossiliscope! The clocks seem to have a weird behaviour and this behaviour changes time to time. For example maybe on one board there is no problem and on the other one there is. And sometimes adding or removing some ILAs (for debugging my design) changes the behaviour!

To the best of my knowledge, I have made correct timing constraints (I mean create output clocks, set output delay and ... regarding my timing behaviour) for output paths but I see this confusing manner. 

Should I pay attention to anything else that I haven't done yet? Is my output path for output clock (ODDR + OBUFDS) correct? And of course any hint or reccomendation is highly appreciated, because I have tested lots of ways to correct this but I haven't reached to any good solution and I feel like I'm stuck in a deadlock.

Here are some information about my design which may be useful:

Device: Kintex-7

Software: Vivado 2017.4

Output Clocks Frequencies: 172 and 43 MHz

Regards,

Herman Fisher

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6 Replies
320 Views
Registered: ‎01-22-2015

Re: Differential Clock Output

Hi Herman!

We can solve this! 

If your HDL is creating the ODDR and the OBUFDS and connecting them properly between the clock source and the FPGA pins then things should be working.  When you open your implemented design for the differential clock output, does it look like the following?
LVDS_CLK.jpg

Next, you need to use an LVDS pin-pair for LVDS output.  OBUFDS.O connects to P-pin, OBUFDS.OB connects to N-pin.  Are you doing this?

Next check your XDC file constraints.  If your LVDS output is in HP bank then you should have constraints that look like the following:

set_property IOSTANDARD LVDS [get_ports SSO3_CLK_P]
set_property PACKAGE_PIN V4 [get_ports SSO3_CLK_P]
set_property IOSTANDARD LVDS [get_ports SSO3_CLK_N]
set_property PACKAGE_PIN W4 [get_ports SSO3_CLK_N]

If your LVDS output is in an HR bank powered by 2.5V then the above constraints should say LVDS_25 instead of LVDS.

What are your LVDS outputs connected with?   -and are they AC-coupled as shown in image below?  -and if they are AC-coupled, where in the circuit are you probing the with your oscilloscope?
LVDS_AC_coupled.jpg

Cheers,
Mark

Contributor
Contributor
307 Views
Registered: ‎12-10-2018

Re: Differential Clock Output

Mark, thanks for your response!

About your questions: I have to say yes, the implemented design has a same structure with the image you attached, and I'm using a LVDS output for the pins as you said, and the corresponding XDC commands are added correctly.

About the last part of your answer (AC coupling) I'm not sure and I have to check it out. Do you think weird behaviour (as I said before the behaviour changes project by project, I mean by two separate implementations with different ILAs added, and different behaviour from a board to another one) may be related to a fault in hardware? Because there are bitstreams which run correctly on every board.

Thanks in advance,

Herman

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295 Views
Registered: ‎01-22-2015

Re: Differential Clock Output

    Because there are bitstreams which run correctly on every board.
Do you mean that for every board there is a project that gives proper LVDS output?

If you remove ILA from all projects, do you get proper LVDS output on every board?

    The clocks seem to have a weird behaviour and this behaviour changes time to time
Please give details of this "weird behaviour" - maybe a photo of the oscope screen

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Contributor
Contributor
256 Views
Registered: ‎12-10-2018

Re: Differential Clock Output

Yes, I mean there are projects that the output clocks are right. But I want to debug my project, so I add some ILAs and remove the others. The generated bitstream works on a board, but not on the other one. And you know this correct project has some different ILAs too. This makes me really confused!

Please give details of this "weird behaviour" - maybe a photo of the oscope screen


By weird behavior, I mean this definitely: I have two clocks with frequencies 43 and 172 MHz. When I program the board, I check the 172 MHz clock using oscilloscope and its frequency is about 240 MHz, it's not a precise frequency and it has frequent changes. And about the 43 MHz clock, approximately I see nothing but a noise! 

I know this situation seems too weird and I really need help with this. So any help would be greatly appreciated. 

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Scholar dgisselq
Scholar
250 Views
Registered: ‎05-21-2015

Re: Differential Clock Output

@hermanfisher1994,

May I ask how you are generating the clocks?  PLL or MMCM or ... other?  And if PLL or MMCM, have you checked the lock indicator at the output to see if the locks were properly created internal to the FPGA in the first place?

Dan

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234 Views
Registered: ‎01-22-2015

Re: Differential Clock Output

@hermanfisher1994 

If you remove all ILAs from the project, does the project then work correctly on all the boards?

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