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Observer alexry
Observer
656 Views
Registered: ‎04-16-2018

Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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In 2018.1 with a Kintex7 part, I've made an example design (attached) which confirms that I am getting different Discrete Jitter values for two identically configured PLLs.  One from a PLL2_BASE primitive and one with a Clocking Wizard IP core.  I've examined the cell properties of both PLLs and I can't see any differences, but in the paths that they time, the clock uncertainty is different due to different Discrete Jitter values being reported.

The PLL primitive reports 63ps of Discrete Jitter (47ps clock uncertainty) while the Clocking Wizard PLL reports 252ps of Discrete Jitter (131ps clock uncertainty).  The 252ps of DJ matches the value reported in the Clocking Wizard summary tab.  

I've left the Clocking Wizard's input jitter setting at 0.01UI (400ps) and have added a set_input_jitter constraint of 400ps for the PLL primitive input clock to match.

I am very interested in the reason for this discrepancy.

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1 Solution

Accepted Solutions
Adventurer
Adventurer
529 Views
Registered: ‎10-24-2008

Re: Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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@alexryThanks for bringing this issue to the attention of the factory.  This is indeed a bug with the timing engine and a CR has been filed to ensure that this is corrected in a future release. 

--Quenton

4 Replies
Observer alexry
Observer
611 Views
Registered: ‎04-16-2018

Re: Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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Reup?

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Explorer
Explorer
600 Views
Registered: ‎07-18-2018

Re: Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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Hi Alexry,

    You are using different primitives. The CLK WIZ is using the ADV and your code is using the BASE

I swapped out the BASE for the advance with the same settings as the Wizard:

PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(36),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(40.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(9),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
PLL_25_rtl
(.CLKFBIN(rtl_pll_fb),
.CLKFBOUT(rtl_pll_fb),
.CLKIN1(clk25_rtl),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_100_rtl),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(),
.DRDY(),
.DWE(1'b0),
.LOCKED(rtl_pll_locked),
.PWRDWN(1'b0),
.RST(reset));

And then the Implemented results match:

CLK_RTL.PNGRTL PLLCLK_WIZ.PNGCLOCK WIZ PLL

Why the BASE with the same apparent settings has less jitter is unclear, there is likely a property or setting that needs to be set, or isn't being set by using the Base primitive. The Wizard seems to always choose the Advance. But they both map to the same primitives (PLLE2_ADV) as expected regardless.

 

 

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Observer alexry
Observer
593 Views
Registered: ‎04-16-2018

Re: Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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Interesting @evant_nq

I've narrowed this down further and see that the discrepancy is having a value of 0.0 or 10.0 for the CLKIN2_PERIOD attribute.  With a value of 0.0, I see the same DJ of 252ps reported on both PLLs.  However, if a value of 10.0 is used (what Vivado auto-populates if a PLL2_BASE primitive is used), the DJ is 63ps.  

This discrepancy is cause by a setting on a clock that isn't even used.  This feels even more like a bug.

@Xilinx ?

Adventurer
Adventurer
530 Views
Registered: ‎10-24-2008

Re: Discrete Jitter discrepancy between PLL primitive and PLL from Clocking Wizard

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@alexryThanks for bringing this issue to the attention of the factory.  This is indeed a bug with the timing engine and a CR has been filed to ensure that this is corrected in a future release. 

--Quenton