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buddha1987
Voyager
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Registered: ‎10-25-2012

Do I have to rerun the implementation to see the STA results with new timing constrain?

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If I opened a implemented design and see my design timing fails in some paths, then I edit my timing constrain in XDC. Do I have to rerun the implementation to see the new STA result? Is there any approach that I see the effects of my new timing constrain?

Thanks in advance.

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

No. That's one of the great things about Vivado...

 

Particularly in project mode, though, you have to understand how constraints work.

 

In Vivado, you can get a design "in memory" - as is done by "opening the elaborated design". When that is done, the placed and routed netlist that was generated during the implementation phase is loaded into memory. At the same time, the XDC files specified by the constraint set (constr_1) are also read in and applied to the design in memory.

 

At this point, if you do any timing reports (report_timing, report_timing_summary) either from the Tcl console or via the flow navigator or menus, you are doing timing reports based on the design in memory and the constraints in memory.

 

At this point, you can change the constraints in memory either by

  - typing the XDC commands into the Tcl console

  - using the Constraints Window to modify the constraints

 

If you do either of these things, then you have changed the constraints that are in memory. At this point, if you do a report_timing (or other report) then the report will be generated with respect to the modified constraints. This can be very powerful when, for example, you implement a design, and realize the worst path was supposed to be false or multicycle - you can "try out" the correct constraint and see what effect it has on the current design.

 

BUT...

 

You need to be aware of a couple of things. First, the new constraints are in memory - they are not in the project files. What this means is that if you close the design (which will happen if you exit the tool, or try and run a new process - like re-running implementation), then the constraints in memory will be lost. The tool will first ask you if you want to "Save the design", and if you say "yes" it will write the constraints you modified (in memory) back to the XDC files which are part of the project. Be aware that this may change the format of your original XDC file as the tool writes it back.

 

Second, even though you have changed the constraints and analyzed your design according to the new constraints, the design was still synthesized, placed, and routed using the old constraints. In general, this means that you should change the XDC files, either by letting the tool save them, or by editting them manually, and then re-run synthesis and implementation.

 

Avrum

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avrumw
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Guide
16,561 Views
Registered: ‎01-23-2009

No. That's one of the great things about Vivado...

 

Particularly in project mode, though, you have to understand how constraints work.

 

In Vivado, you can get a design "in memory" - as is done by "opening the elaborated design". When that is done, the placed and routed netlist that was generated during the implementation phase is loaded into memory. At the same time, the XDC files specified by the constraint set (constr_1) are also read in and applied to the design in memory.

 

At this point, if you do any timing reports (report_timing, report_timing_summary) either from the Tcl console or via the flow navigator or menus, you are doing timing reports based on the design in memory and the constraints in memory.

 

At this point, you can change the constraints in memory either by

  - typing the XDC commands into the Tcl console

  - using the Constraints Window to modify the constraints

 

If you do either of these things, then you have changed the constraints that are in memory. At this point, if you do a report_timing (or other report) then the report will be generated with respect to the modified constraints. This can be very powerful when, for example, you implement a design, and realize the worst path was supposed to be false or multicycle - you can "try out" the correct constraint and see what effect it has on the current design.

 

BUT...

 

You need to be aware of a couple of things. First, the new constraints are in memory - they are not in the project files. What this means is that if you close the design (which will happen if you exit the tool, or try and run a new process - like re-running implementation), then the constraints in memory will be lost. The tool will first ask you if you want to "Save the design", and if you say "yes" it will write the constraints you modified (in memory) back to the XDC files which are part of the project. Be aware that this may change the format of your original XDC file as the tool writes it back.

 

Second, even though you have changed the constraints and analyzed your design according to the new constraints, the design was still synthesized, placed, and routed using the old constraints. In general, this means that you should change the XDC files, either by letting the tool save them, or by editting them manually, and then re-run synthesis and implementation.

 

Avrum

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buddha1987
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Registered: ‎10-25-2012

Thanks very much, avrumw.

I have following two questions:

1. If I opened a design, and I saw a failed path should be false path. In this case, I need to input tcl or using GUI to add constrain in Memory, then I rerun the report timing I can see new reports. Editing constrain in xdc file will not work since the modification is not in Memory, right?

 

2. Even I edited the constrains in memory after I open a design, I regenerate the report, but this report is still based on old implemented (or synthesised) design but with updated constrains. Therefore, the timing analysis in this case may not be accurate since the implemented (or synthesised) design is still old, right? My understanding is constrains may affect synthesis and implmentation. So if constrain has been changed, even HDL keeps but the design may still synthessied or implmemnted different.

 

Thanks in advance.

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

1) Yes

 

2) Mostly. You said that if you change the constraints then the timing analysis is "not accurate". Its not the timing analysis that isn't accurate, its that the design was optimized using the wrong constraints - the structure and placement and routing of the design was done using the old constraints. The new analysis is an accurate representation of how the currently placed design will behave with the new constraints.

However, if you save the changed constraints and then re-run synthesis and implementation, you will get a new version of your design that is optimized with the new constraints, which may have better timing and/or area.

 

Avrum

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buddha1987
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Registered: ‎10-25-2012
Thanks very much, Avrum.

For Q2, yes, that is what I mean.
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