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jbaxley
Newbie
Newbie
437 Views
Registered: ‎01-21-2021

Duplicate clocks from clocking wizard

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I am using Vivado 2019.1 and creating a design for a Digilent Nexys 4 DDR. I pass the on-board clock to the clocking wizard to create 3 clocks for my design. In timing analysis all 3 of these clocks are repeated twice. Does anyone know why this happens or how to solve it? I don't think it's actually causing any problems but it makes the timing report a bit more complicated. I've tried deleting and recreating the clocking wizard.

My instantiation:

clk_wiz_top clk_wiz_top_inst(
        .clk_in100(CLK100MHZ),
        .clk_out_50(clk_eth_phy_ref),
        .clk_core(clk_core),    
        .clk_stack(clk_stack)    
    );

Schematic:

image.png

 

Constraint:

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK100MHZ]

 report_clocks:

Clock                        Period(ns)  Waveform(ns)    Attributes  Sources
CLK100MHZ                    10.000      {0.000 5.000}   P           {CLK100MHZ}
ether/maccy/inst/mii_rx_clk  40.000      {0.000 20.000}  P           {ether/maccy/inst/mii_rx_clk}
ether/maccy/inst/mii_tx_clk  40.000      {0.000 20.000}  P           {ether/maccy/inst/mii_tx_clk}
sys_clk_pin                  10.000      {0.000 5.000}   P           {CLK100MHZ}
clk_core_clk_wiz_top         6.667       {0.000 3.333}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT1}
clk_core_clk_wiz_top_1       6.667       {0.000 3.333}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT1}
clk_out_50_clk_wiz_top       20.000      {0.000 10.000}  P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT0}
clk_out_50_clk_wiz_top_1     20.000      {0.000 10.000}  P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT0}
clk_stack_clk_wiz_top        10.000      {0.000 5.000}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT2}
clk_stack_clk_wiz_top_1      10.000      {0.000 5.000}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT2}
clkfbout_clk_wiz_top         10.000      {0.000 5.000}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKFBOUT}
clkfbout_clk_wiz_top_1       10.000      {0.000 5.000}   P,G,A       {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKFBOUT}


====================================================
Generated Clocks
====================================================

Generated Clock     : clk_core_clk_wiz_top
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : CLK100MHZ
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 -1.667 -3.333}
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT1}

Generated Clock     : clk_core_clk_wiz_top_1
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : sys_clk_pin
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 -1.667 -3.333}
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT1}

Generated Clock     : clk_out_50_clk_wiz_top
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : CLK100MHZ
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 5.000 10.000}
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT0}

Generated Clock     : clk_out_50_clk_wiz_top_1
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : sys_clk_pin
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 5.000 10.000}
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT0}

Generated Clock     : clk_stack_clk_wiz_top
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : CLK100MHZ
Multiply By         : 1
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT2}

Generated Clock     : clk_stack_clk_wiz_top_1
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : sys_clk_pin
Multiply By         : 1
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKOUT2}

Generated Clock     : clkfbout_clk_wiz_top
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : CLK100MHZ
Multiply By         : 1
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKFBOUT}

Generated Clock     : clkfbout_clk_wiz_top_1
Master Source       : clk_wiz_top_inst/inst/mmcm_adv_inst/CLKIN1
Master Clock        : sys_clk_pin
Multiply By         : 1
Generated Sources   : {clk_wiz_top_inst/inst/mmcm_adv_inst/CLKFBOUT}

 

 

 

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Accepted Solutions
joancab
Teacher
Teacher
407 Views
Registered: ‎05-11-2015

Wait... you have those two source clocks CLK100MHZ and sys_clk_pin, isn't one of those redundant?

View solution in original post

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6 Replies
joancab
Teacher
Teacher
433 Views
Registered: ‎05-11-2015

I'd say they are not duplicated but refer to the nets before and after the BUFG. I suppose because of the time constraints they are both analyzed. Try dropping one of the buffers and see if the duplication goes away.

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jbaxley
Newbie
Newbie
420 Views
Registered: ‎01-21-2021

Ok, I'll try to just ignore it. I've just never seen this before on other similar designs, and it was confusing at first to see inter-clock paths between a clock and itself.

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joancab
Teacher
Teacher
408 Views
Registered: ‎05-11-2015

Wait... you have those two source clocks CLK100MHZ and sys_clk_pin, isn't one of those redundant?

View solution in original post

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jbaxley
Newbie
Newbie
379 Views
Registered: ‎01-21-2021

Thanks! I changed 'sys_clk_pin' to 'CLK100MHZ' and it's fixed now. I had just copied and pasted the constraints from Digilent.

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360 Views
Registered: ‎01-22-2015

@jbaxley 

In timing analysis all 3 of these clocks are repeated twice.

This is because both you and the Clocking Wizard wrote create_clock constraints for the clock entering the FPGA on port CLK100MHz.  Further, because your create_clock constraint used the -add option, two 100MHz clocks were created.  Creating two clocks on an FPGA pin/port is allowed in Vivado - but is not what you intended (I think).

The solution is to erase the create_clock constraint that you wrote - and let the create_clock constraint written by the Clocking Wizard create the 100MHz clock.

The create_clock constraint written by the Clocking Wizard is hidden in a .xdc file that is associated with the Clocking Wizard IP.

Cheers,
Mark

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avrumw
Expert
Expert
354 Views
Registered: ‎01-23-2009

Here's what's happening.

When you create a clock module with the clocking wizard, it is treated as IP. Like all other IP, this clocking IP has constraints. If you open the constraint file associated with the wizard, you will find that the constraint wizard created a clock on the clkin_100 port of the clocking wizard named CLK100MHZ. It got the information for creating this clock from the information you entered in the clocking wizard dialog box.

When this IP gets read in, the clock constraint on the port of the clocking wizard gets back propagated to the port of the design - the port named CLK100MHZ

Then you added a create_clock in your user XDC file. Here you specified a clock on the CLK100MHZ port directly. You gave it a different name (which is legal), and you put the -add option.

By default a port/net/pin can carry only one clock. However, if you use the create_clock with the -add option, this says "instead of replacing the clock that already exists on this port/pin/net (and downstream of it), add this clock. So now the port/net/pin (in your case port) carries both clocks. Both of these clocks propagate through the MMCM and generate two sets of output clocks.

Now as to why what you did fixed it...

While a port/pin/net can carry more than one clock, it is not possible to have multiple clocks in the design database with the same name. So when you changed the name of your manually created clock to match the name of the clock generated by the clocking wizard, the new clock overrode the clock of the same name. This is independent of the -add option; the second clock with the same name removes the first one from the design database.

So, the solution is don't use the -add option. For some reason many templates from Xilinx show the -add option. In most circumstances, you do not want to have multiple clocks on the same net/pin/port - therefore you shouldn't use the -add option unless there is a specific reason to do so. (The same is true of the -add_delay option to the set_input_delay/set_output_delay - many Xilinx generated templates and examples use this, but it does a similar thing... the -add_delay should only be used if it is specifically necessary).

Avrum

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