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Scholar ronnywebers
Scholar
8,017 Views
Registered: ‎10-10-2014

Edge-Aligned Dual Data Rate Source Synchronous Inputs - skew values positive or negative

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Hello,

 

please refer to the screenshot of an example datasheet. It shows a clock & data bus, which enters the FPGA and goes into a IDDR. It's actually an RMII interface entering the FPGA

 

I'm confused by the 'direction' of timing constraints in Vivado vs datasheets

 

If I look at the template below, for example skew_bre, has an arrow pointing in 2 directions. If I look at the datasheet, there's a min value (-0.5), meaning data previous data will be stable until at least 0.5ns before the clock edge, and a max value (+0.5) meaning next data will be available at latest  max 0.5 ns after the clock edge (hope I'm expressing this correctly too :-). Datasheets sometimes draw the setup time with an arrow to the left, and the hold time with an arrow to the right. Is there some convention on this?

 

How do the values from the datasheet screenshot translate to the xdc  template? Is the following correct , asuming a clock period of 8ns?

where my doutbs are is for example : skew_bre = -0.500ns, or + 0.500ns? 

 

 

# Edge-Aligned Dual Data Rate Source Synchronous Inputs
# (Using a direct FF connection)
#
# For an edge-aligned Source Synchronous interface, the clock
# transition occurs at the same time as the data transitions.
# In this template, the clock is aligned with the beginning of the
# data. The constraints below rely on the default timing
# analysis (setup = 1/2 cycle, hold = 0 cycle).
#
# input            _________________________________
# clock  _________|                                 |___________________________
#                 |                                 |                 
#         skew_bre|skew_are                 skew_bfe|skew_afe
#         <------>|<------>                 <------>|<------>
#        _        |        _________________        |        _________________
# data   _XXXXXXXXXXXXXXXXX____Rise_Data____XXXXXXXXXXXXXXXXX____Fall_Data____XX
#

set input_clock         <clock_name>;      # Name of input clock
set input_clock_period  8.000;    		   # Period of input clock (full-period)
set skew_bre           -0.500;             # Data invalid before the rising clock edge
set skew_are            0.600;             # Data invalid after the rising clock edge
set skew_bfe           -0.500;             # Data invalid before the falling clock edge
set skew_afe            0.600;             # Data invalid after the falling clock edge
set input_ports         <input_ports>;     # List of input ports

# Input Delay Constraint 
# --- EMPTY TEMPLATE ---
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 + $skew_afe] [get_ports $input_ports];
set_input_delay -clock $input_clock -min [expr $input_clock_period/2 - $skew_bfe] [get_ports $input_ports];
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 + $skew_are] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min [expr $input_clock_period/2 - $skew_bre] [get_ports $input_ports] -clock_fall -add_delay;

# --- NOW WITH VALUES FILLED IN ---
set_input_delay -clock $input_clock -max [8/2 + 0.6] [get_ports $input_ports];
set_input_delay -clock $input_clock -min [8/2 - (-0.5)] [get_ports $input_ports];
set_input_delay -clock $input_clock -max [8/2 + 0.6] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min [8/2 - (-0.5)] [get_ports $input_ports] -clock_fall -add_delay;

# --- NOW WITH VALUES CALCULATED ---
set_input_delay -clock $input_clock -max 4.6 [get_ports $input_ports];
set_input_delay -clock $input_clock -min 4.5 [get_ports $input_ports];
set_input_delay -clock $input_clock -max 4.6 [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min 4.5 [get_ports $input_ports] -clock_fall -add_delay;

# Report Timing Template
# report_timing -rise_from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_ddr_in_rise -file src_sync_edge_ddr_in_rise.txt;
# report_timing -fall_from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_ddr_in_fall -file src_sync_edge_ddr_in_fall.txt;
          
        
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input timing.jpg
input timing numbers.jpg
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Historian
Historian
15,370 Views
Registered: ‎01-23-2009

Re: Edge-Aligned Dual Data Rate Source Synchronous Inputs - skew values positive or negative

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No, the sign of the skew_bre is wrong...

 

In this template, it assumes the skew_are is positive going toward the right and the skew_bre is positive toward the left. 

 

This is often inconsistent with how devices with edge aligned interfaces spec their outputs, which measure the clock/data skew with the positive direction always going to the right (increasing time) - as your RMII does.

 

You can (more or less) see the values you are using are incorrect - the minus signs in the equations mask, thus saying that the min delay is 8/4+0.5 and the max is 8/4+0.6. This essentially says that the data changes somewhere between these two values, which means that it is only unknown for 0.1ns. This is clearly inconsistent with your RMII spec that says that it is unknown for 1.1ns.

 

I am also not a terrible fan of this template - it uses what I refer to as the "cheater" way for specifying this interface. For a complete description of how this interface is/should be constrained, see this post.

 

Avrum

 

 

2 Replies
Historian
Historian
15,371 Views
Registered: ‎01-23-2009

Re: Edge-Aligned Dual Data Rate Source Synchronous Inputs - skew values positive or negative

Jump to solution

No, the sign of the skew_bre is wrong...

 

In this template, it assumes the skew_are is positive going toward the right and the skew_bre is positive toward the left. 

 

This is often inconsistent with how devices with edge aligned interfaces spec their outputs, which measure the clock/data skew with the positive direction always going to the right (increasing time) - as your RMII does.

 

You can (more or less) see the values you are using are incorrect - the minus signs in the equations mask, thus saying that the min delay is 8/4+0.5 and the max is 8/4+0.6. This essentially says that the data changes somewhere between these two values, which means that it is only unknown for 0.1ns. This is clearly inconsistent with your RMII spec that says that it is unknown for 1.1ns.

 

I am also not a terrible fan of this template - it uses what I refer to as the "cheater" way for specifying this interface. For a complete description of how this interface is/should be constrained, see this post.

 

Avrum

 

 

Highlighted
Scholar ronnywebers
Scholar
7,999 Views
Registered: ‎10-10-2014

Re: Edge-Aligned Dual Data Rate Source Synchronous Inputs - skew values positive or negative

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thanks @avrumw for the very clear answer - the remark you made on the 'only' 0.1ns uncertainty made me understand my mistake :-)

 

I'll check your other post immediately - it looks very interesting, but I'll need some time to digest it I guess :-)

 

I'm actually trying to setup the constraints on a GMII to RMII interface (using Xilinx IP block) that connects GEM1 of the ARM with a 2nd external phy on our board through the EMIO pins. I'm stuck on the timing closure now for days, trying to get the constraints and the IDELAY values on the data lines right :-(

 

Just for completeness I'm posting the corrected version of the constraints. I also added a '0' and '+' sign in in the waveform to indicate the 'positive direction' :

# input            _________________________________
# clock  _________|                                 |___________________________
#                 |                                 |                 
#         skew_bre|skew_are                 skew_bfe|skew_afe
#       + <------0|0------> +             + <------0|0------> +
#        _        |        _________________        |        _________________
# data   _XXXXXXXXXXXXXXXXX____Rise_Data____XXXXXXXXXXXXXXXXX____Fall_Data____XX
#

so the corrected template would be :

# Edge-Aligned Dual Data Rate Source Synchronous Inputs
# (Using a direct FF connection)
#
# For an edge-aligned Source Synchronous interface, the clock
# transition occurs at the same time as the data transitions.
# In this template, the clock is aligned with the beginning of the
# data. The constraints below rely on the default timing
# analysis (setup = 1/2 cycle, hold = 0 cycle).
#
# input            _________________________________
# clock  _________|                                 |___________________________
#                 |                                 |                 
#         skew_bre|skew_are                 skew_bfe|skew_afe
#       + <------0|0------> +             + <------0|0------> +
#        _        |        _________________        |        _________________
# data   _XXXXXXXXXXXXXXXXX____Rise_Data____XXXXXXXXXXXXXXXXX____Fall_Data____XX
#

set input_clock         <clock_name>;      # Name of input clock
set input_clock_period  8.000;    		   # Period of input clock (full-period)
set skew_bre            0.500;             # Data invalid before the rising clock edge
set skew_are            0.600;             # Data invalid after the rising clock edge
set skew_bfe            0.500;             # Data invalid before the falling clock edge
set skew_afe            0.600;             # Data invalid after the falling clock edge
set input_ports         <input_ports>;     # List of input ports

# Input Delay Constraint 
# --- EMPTY TEMPLATE ---
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 + $skew_afe] [get_ports $input_ports];
set_input_delay -clock $input_clock -min [expr $input_clock_period/2 - $skew_bfe] [get_ports $input_ports];
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 + $skew_are] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min [expr $input_clock_period/2 - $skew_bre] [get_ports $input_ports] -clock_fall -add_delay;

# --- NOW WITH VALUES FILLED IN ---
set_input_delay -clock $input_clock -max [8/2 + 0.6] [get_ports $input_ports];
set_input_delay -clock $input_clock -min [8/2 - 0.5] [get_ports $input_ports];
set_input_delay -clock $input_clock -max [8/2 + 0.6] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min [8/2 - 0.5] [get_ports $input_ports] -clock_fall -add_delay;

# --- NOW WITH VALUES CALCULATED ---
set_input_delay -clock $input_clock -max 4.6 [get_ports $input_ports];
set_input_delay -clock $input_clock -min 3.5 [get_ports $input_ports];
set_input_delay -clock $input_clock -max 4.6 [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min 3.5 [get_ports $input_ports] -clock_fall -add_delay;

# Report Timing Template
# report_timing -rise_from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_ddr_in_rise -file src_sync_edge_ddr_in_rise.txt;
# report_timing -fall_from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_ddr_in_fall -file src_sync_edge_ddr_in_fall.txt;
          
        

 

 

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