UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer s_aelsok
Observer
8,200 Views
Registered: ‎03-19-2012

Explanation needed - slight delay reduction after adding dummy register

Hi all,

 

I was implementing a 16k point FFT on a virtex-6 FPGA (on ML605). I wanted to meet a timing constraint of 4.069 ns to run at the clock speed of my ADC (FMC150 AD/DA) . 

 

I used a block RAM (used as ROM) to store my twiddle factors. this ROM is followed by a complex multiplier.  First, the design would not meet the constraint (post PAR timing report), and the min clock period achievable was 4.270 ns.

 

I added a register between the block RAM (twiddle factor ROM) and the complex multiplier, and I could meet the constraint. The minimum period was slightly reduced to 4.071. (difference of 0.002 ns higher than my constraint) however, the post PAR timing report says that all constraints were met.  Note that there was no change in the synthesis results regarding max. frequency.

 

Any explanation of this delay reduction by adding such a register ?

 

 

In case it helps, ROM code is attached.

 

Best regards,

Ahmed.

0 Kudos