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Visitor alienchang
Visitor
6,037 Views
Registered: ‎02-04-2009

External deskew : virtex-5

Hi all,

 

I am trying to use external deskew for my virtex-5 , because I need to propagate clock and data to outside chip.

I use two DCMs such as Figure 2-13 in UG190 (please see below picture).

If Q0 is clocked by BUFG_W0 and Q1 is clocked by BUFG_W1.

If I constraint BUFG_W0 and BUFG_W1 are relative like below:

NET "BUFG_W0" TNM_NET = "BUFG_W0";

TIMESPEC "TS_BUFG_W0" = PERIOD "BUFG_W0" 23.809 ns HIGH 50.00%;
NET "BUFG_W1" TNM_NET = "BUFG_W1";
TIMESPEC "TS_BUFG_W1" = PERIOD "BUFG_W1" "TS_BUFG_W0" * 1.000000 HIGH 50.00%;

 

Why did I get a hold violation result for path from Q0 to Q1?

These flip-flops should be routed in low skew path, right?

Did xilinx not deskew these two clocks ?

 

Should I use synchronization circuit for this path?

 

 

 

Another problem is this warning:

WARNING:Timing:3262 - Feedback on DCM or PLL CLKDLL_MCK1X1/DCM_ADV forms an incomplete loop. The Tdcmino calculation
   will be invalid. If the DCM or PLL uses external feedback, please apply the FEEDBACK constraint to indicate the
   external board delay. Consult the Constraints Guide for further information on how to apply the FEEDBACK constraint.


 Should I add FEEDBACK constraint when doing PAR? or this constraint is just only use for timing analyze and it doesn't influence the PAR result?

 

 

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2 Replies
Participant jared.chen
Participant
5,846 Views
Registered: ‎05-12-2008

Re: External deskew : virtex-5

The clock BUFG_W0 has different phase from BUFG_W1. I think you should use BUFG_W0 to drive the Q1, and then write an OFFSET OUT constraint to ensure the downstream ASIC can sample the right data.

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Xilinx Employee
Xilinx Employee
5,841 Views
Registered: ‎08-10-2008

Re: External deskew : virtex-5

The DCM compensation value should be invalid. You need to apply the FEEDBACK constraint in the UCF file, so that the corresponding clock deskew can be performed.

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