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Adventurer
Adventurer
180 Views
Registered: ‎11-08-2018

FPGA ARTIX 7: Report Timing Summary..WNS--TNS

Hi Everyone,

I have a project about FPGA ARTIX 7 at35 csg 324 -1L,

When I connected the system and Bitstream

It's " Timing 28:282 .Report Timing ".

I have readed some Page and some solution,but I dont know that,

Somebody said " fixing clk_clock example 100hz to 80hz,when The system will meets timing"
I using 2 clock.200Mhz and 166,666 Mhz.166,666Mhz is system clock.
So about 200mhz clock,what is it related to ?

If you have some solution please tell me,

Thank you very much,

tuan,

 

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3 Replies
Explorer
Explorer
155 Views
Registered: ‎07-18-2018

Re: FPGA ARTIX 7: Report Timing Summary..WNS--TNS

Hi tuan94@,

    I am a little confused as to the following:

 

Somebody said " fixing clk_clock example 100hz to 80hz,when The system will meets timing"

Who said this, and in what context? Slowing down a clock can aleviate timing issues, but without context that might not be a tennable soultion. Is this an example design you are using?

I using 2 clock.200Mhz and 166,666 Mhz.166,666Mhz is system clock.
So about 200mhz clock,what is it related to ?

What do you mean by a 200Mhz and 166Mhz clock? Are these both coming into the board as independent clocks? Are they driving independent logic?

The failure seems to be within the 166Mhz domain. So the comment about 200Mhz is a little confusing?

Maybe a little more context to those two statments can help people provide suggestions!

 

 

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Adventurer
Adventurer
141 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7: Report Timing Summary..WNS--TNS

Hi ,

Thank your answer,

Do you see this problem the same with :
https://forums.xilinx.com/t5/Timing-Analysis/FPGA-ARTIX-7-Report-Timing-Summary/m-p/940893#M16104
I just want to fix that error.But I don't know how to fix that.

Your question 1:It's hard to understand and tell you know my way.

Your question 2:I think we dont need to care about 200Mhz clock,I use this clock for some Port.

Thank you very much,

tuan,

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Adventurer
Adventurer
120 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7: Report Timing Summary..WNS--TNS

Hi,

I dont know why ?

About System_clock  166,667 Mhz, 200Mhz(different)

When I had change system_clock 166,667Mhz so the value of clock 200 Mhz is also changed 

but Some value make clock 200Mhz,dont change

Example : use 135.000 Mhz -- 200mhz,175.000Mhz --198.000 Mhz,166.666Mhz--200Mhz
Surprising when I using 135 Mhz so the system make meets timing about 200Mhz
but Clock 200Mhz,System not make meets timing.

I dont know clearly,If you know some info please tell me

thank you very much,

tuan,  

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