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Explorer
Explorer
1,180 Views
Registered: ‎10-12-2018

FPGA with two synchronous clock input

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Hi All,

I have an FPGA with two synchronous, 100Mhz clock in-port (clkA, and clkB). The two clock comes from one source, but via different driver and path, so the phase can differ in a given interval. The clkA can arrive 0.5ns earlyer, and 1.0 ns later in worst case. This is not a jitter: both clock are low jitter clocks. This phase difference can occure board-to-board or can wander slowly due to temperature, etc.

image.png

 

So the Intra-Clock Path of both clock should be calculated with 10ns period time (100MHz) (reg1 -> reg2 and reg3 -> reg4), (again this delay is not a jutter)

But the Inter-Clock Path should be calculated using the worst (-0.5 ... 1.0) clock delays (reg2 -> reg3),.

How can I constraint this case?

 

I have tried something like this:

 

create_clock -period 10.000 -name clkA [get_ports i_clkA]
create_clock -period 10.000 -name clkB [get_ports i_clkB]

set_clock_latency -min -source  -0.5 [get_pins i_clkA]
set_clock_latency -max -source  1.0 [get_pins i_clkA]

The Inter-Clock Paths are calculated perfectly using these constraints, BUT the Timing report assumed (in the Intra-Clock paths of clkA) that the latency of the clkA can differ period by period, like a jitter, or uncerteanity, however it's not true.

image.png

 

Should I add min/max delay on the Inter clock paths? (In this case the internal clock delays, can cause problems.)

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Explorer
Explorer
1,138 Views
Registered: ‎10-12-2018

I found that I can use min/max delay. (I didn't understand them correctly.) 

set_min_delay 1 -from $clkA -to $clkB
set_max_delay [expr 10 - 0.5]  -from $clkA -to $clkB

Now everithing is perfect.

(Note, that traditional CDC is not acceptable in my application due to required fix delay.)

View solution in original post

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Moderator
Moderator
1,160 Views
Registered: ‎01-16-2013

Hi,

Best case suggestion is to manage reg2 --> reg3 as asynchronous CDC with proper circuit and constraints. Please refer UG949.

Clock is generated using same oscilator still this have phase inconsistency and we cannot consider this as truly synchronous. Using set_max_delay and set_min_delay you can just overide the worst case calculated requirement but 100% assurance you can get with CDC circuit.

Thanks,
Yash

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Scholar
Scholar
1,153 Views
Registered: ‎08-07-2014

@betontalpfa,

I agree with the above solution to treat both clks as async.

Don't forget to use this in your xdc : set_clock_groups -name async_clocks -asynchronous -group [clkA ] [clkB] to disable the inter clock domain analysis & optimization.

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Highlighted
Explorer
Explorer
1,139 Views
Registered: ‎10-12-2018

I found that I can use min/max delay. (I didn't understand them correctly.) 

set_min_delay 1 -from $clkA -to $clkB
set_max_delay [expr 10 - 0.5]  -from $clkA -to $clkB

Now everithing is perfect.

(Note, that traditional CDC is not acceptable in my application due to required fix delay.)

View solution in original post

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Xilinx Employee
Xilinx Employee
1,130 Views
Registered: ‎05-22-2018

Hi @betontalpfa ,

If there is nor specific boundation on using 2 external same clock with different phase.

An other suggestion would be to use Clock Modifying Blocks .i.e., MMCM with one external clock. For more information please check page no. 35 of below link:

https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

Thanks,

Raj

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Explorer
Explorer
1,121 Views
Registered: ‎10-12-2018

Hi @rshekhaw 

Yes, you are right. In an ideal world there is no meaning of using two external source of the same source. Our HW design has some limitation which requires this. This is a Zynq device, which has a dedicated PS clock, which is driven by a poor clockdriver IC. And there is a clock connected directly to FPGA, which has better timings. So I have to use both clocks. However there are several solution, this seems the simplest, which works now.

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Guide
Guide
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Registered: ‎01-23-2009

First, with the timing you specified (a variation of -0.5 to +1.0) these clocks do not need to be treated as asynchronous (or mesochronous) - they are "synchronous enough" for normal clock crossing (although the tool will end up with some reasonably large hold times problems to deal with - depending on how you do the clock crossing).

Your solution with the set_max_delay and set_min_delay will probably work - these override the normal requirements (which are 10 and 0 for setup and hold respectively). Since you are not using the -datapath_only (which you shouldn't and isn't legal with set_min_delay anyway), then the tools will still analyze clock insertion delay and jitter on both clocks.

Another (maybe cleaner) solution would be to use the set_clock_uncertainty command [Note: I haven't tried this in Vivado, so you would have to test it]. It would look something like this

set_clock_uncertainty -from [get_clocks clkA] -to [get_clocks clkB] -setup 0.5
set_clock_uncertainty -from [get_clocks clkA] -to [get_clocks clkB] -hold 1.0

These should mimic the set_min_delay/set_max_delay that you have. But I have a couple of concerns:

  • Is there data moving from clkB to clkA as well?
    • Your constraints don't cover this path, so they will remain at 10, 0 (for setup hold)
    • I am ot sure what the above commands will do for the clkB->clkA path it will either
      • Use the same combinations (9.5,1) or
      • Leave them alone (10,0), in which case you would need a second set of commands from clkB to clkA
        • set_clock_uncertainty -from [get_clocks clkB] -to [get_clocks clkA] -setup 1.0
          set_clock_uncertainty -from [get_clocks clkB] -to [get_clocks clkA] -hold 0.5

Regardless of which set of commands you use (the set_min_delay/set_max_delay or the set_clock_uncertainty), you are asking the tools to fix an additional 1ns of hold time. It will do this by adding additional routing inside the FPGA on the paths between these two clocks. It should be able to fix the hold times (1ns on 10ns isn't too larger), but it will increase routing delay and routing congestion (so it does come at a cost). You may be able to alleviate this by crossing from positive edge of clkA to negative edge of clkB - this will reduce the setup requirement to 4.5ns, but will totally solve the hold time problem (and extra routing).

Avrum

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Explorer
Explorer
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Registered: ‎10-12-2018

Here is a detailed solution:

 

 

#specify the min/max external clock delay from the global oscillator to clock A input
set clk_a_m 5.713
set clk_a_M 7.720

#specify the min/max external clock delay from the global oscillator to clock B input
set clk_b_m 4.048
set clk_b_M 4.455

set a_clk [get_clocks sys_a_100]
set b_clk [get_clocks sys_b_100]

#
# Specify delays    b_clk - >>> - a_clk
#
set b_to_a_delay_m [expr $clk_a_M - $clk_b_m]
set b_to_a_delay_M [expr $clk_a_m - $clk_b_M + 10]
set_min_delay $b_to_a_delay_m -from $b_clk -to $a_clk
set_max_delay $b_to_a_delay_M -from $b_clk -to $a_clk

#
# Specify delays    a_clk - >>> - b_clk
#
set a_to_b_delay_m [expr $clk_b_M - $clk_a_m]
set a_to_b_delay_M [expr $clk_b_m - $clk_a_M + 10]
set_min_delay $a_to_b_delay_m   -from $a_clk -to $b_clk
set_max_delay $a_to_b_delay_M   -from $a_clk -to $b_clk

 

 

 

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Participant
Participant
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Registered: ‎04-03-2017

> Don't forget to use this in your xdc : set_clock_groups -name async_clocks -asynchronous -group [clkA ] [clkB] to disable the inter clock domain analysis & optimization

 

Don't you want some kind of timing analysis on your CDC's?  I think using set_max_delay [...] --datapath_only is almost always more appropriate.

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Explorer
Explorer
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Registered: ‎10-12-2018

Hi @avrumw 

I know this is an old thread, however I want answer some of your ideas/question.

Is there data moving from clkB to clkA as well? (Your constraints don't cover this path, so they will remain at 10, 0 (for setup hold))

In the real design: YES, but I want as simple example as possible. Similar min/max delay constraints can be written to cover this path.

The set_clock_uncertainty command does not accept negative numbers. (The uncertainty cannot be negative.) However, the delays will be negative in one of the directions. (It must be if you calculate all the four delays.) Therefore the data valid window cannot be slipped, only reduced.

So the set_min/max_delay is a more general tool for this use-case.

Benedek