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havendream
Visitor
Visitor
12,441 Views
Registered: ‎06-25-2012

Failed to use DCM locked signal as reset

I want to use the "locked" signal of the DCM output as the reset for the internal logic. As the datasheet said, it takes some time for the locked signal to be valid. 

 

So I use reset = not locked (valid high). But it doesn't work. It seems that the locked signal is always high. It doesn't experience a low to high process as expected.

 

What can be the reason? 

 

The FPGA I used is virtex4 vsx35.

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havendream
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Registered: ‎06-25-2012

forget to say, I want to use the locked signal to achieve automatical reset after power up. 

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ditiris
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12,423 Views
Registered: ‎11-27-2007

So I use reset = not locked (valid high). But it doesn't work. It seems that the locked signal is always high. It doesn't experience a low to high process as expected.

 

How are you measuring this? As you said, the datasheet specifies from tens to hundres of us to achieve lock.

 

Strictly speaking, you don't need to reset the FPGA after power-up.

 

If you need more delay you can use a series of SRLs or a counter.

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havendream
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Registered: ‎06-25-2012

Hi

 

I try different ways to confirm that there is no reset signal.

 

1) I found that some FSM doesn't enter the reset state. This lead me to doubt about the reset signal.

 

2) I drive the locked signal to a PIN and measured with oscillator.

 

3) I write a little code to test. It work like this: a counter is increased at each rising edge of the clock. If the counter reach a specified value, then a LED is lighted up. The value of counter is 0 after configuration, but set to another value (=specified value - 1) when reset is asserted.  So if reset is valid then the LED will light immediately otherwise it will take some time for the counter to count from 0 to the specified value. 

 

If I reset the DCM by the button, then the locked signal will be low and then become high as expected.

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ditiris
Participant
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Registered: ‎11-27-2007

It's unlikely the DCM starts up locked. It's far more likely there is an error in your code and measurement methods.

 

2) I drive the locked signal to a PIN and measured with oscillator.

 

If I reset the DCM by the button, then the locked signal will be low and then become high as expected.

 

I assume you mean an ocsilloscope. So you probe the locked signal forwarded to a pin and trigger off a rising edge and don't get a rising edge on power-up? What is your sampling resolution on the oscilloscope? A button press will drive a signal on the order of milliseconds, which is likely orders of magnitude longer than a DCM will spend unlocked. You can also measure relative to the CONFIG DONE pin, which is sent to an LED on most eval boards.

 

You can always use an SRL with init set to F's, the d set to 0, and ce set to locked to create a longer reset.

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eteam00
Instructor
Instructor
12,405 Views
Registered: ‎07-21-2009

There are two considerations:

  • How does the Virtex-4 DCM behave at initial power-up and configuration
  • How to implement a reliable reset for initialising state following configuration

I hope that progress on your design is not impeded or delayed by the Virtex-4 DCM LOCKED signal mystery.

 

If the Virtex-4 DCM LOCKED signal is not a reliable source for the reset/init function, the practical recourse is to not rely (solely) on it.

 

-- Bob Elkind

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havendream
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Registered: ‎06-25-2012

It's unlikely the DCM starts up locked. It's far more likely there is an error in your code and measurement methods.

I assume you mean an ocsilloscope. So you probe the locked signal forwarded to a pin and trigger off a rising edge and don't get a rising edge on power-up? What is your sampling resolution on the oscilloscope? 

 

The oscilloscope is quite a good one (Lecroy, 600MHz, 10 G/s). The test code is very simple:

 

ENTITY rst_test IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
out1 : OUT std_logic;
out2 : OUT std_logic
);

-- Declarations

END rst_test ;

--
ARCHITECTURE behav OF rst_test IS
signal cnt : std_logic_vector(31 downto 0) := X"00000000";
BEGIN
process(clk,reset)
begin
  if reset = '1' then
 cnt <= X"0BEBC200";
out1 <= '0';
out2 <= '1';
  elsif (RISING_EDGE(clk)) then
cnt <= cnt + 1;
if cnt = X"0BEBC201" then
out1 <= '1';
  end if;
end if;
end process;
END ARCHITECTURE behav;

 

What I can suspect now is that the locked signal is not working as expected unless the DCM itself is reset. Or the DCM is configured first so when other logic are configured the DCM is already locked.


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bassman59
Historian
Historian
12,388 Views
Registered: ‎02-25-2008


@havendream wrote:


 

What I can suspect now is that the locked signal is not working as expected unless the DCM itself is reset. Or the DCM is configured first so when other logic are configured the DCM is already locked.




Well, you DO realize that the DCM needs to be held reset until after its input clock is running?

A simple shift register, initialized to all '1' , shifting in zeros and clocked by the input clock works well. 

----------------------------Yes, I do this for a living.
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sparenteau1
Visitor
Visitor
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Registered: ‎02-21-2013

Hi all, I am new to this forum activities.

I am a little confused with two responses that looked conflicting to me. In one thread I read " Strictly speaking, you don't need to reset the FPGA after power-up." and in the above thread, I read: " Well, you DO realize that the DCM needs to be held reset until after its input clock is running?"

For a Spartan-6, does the FPGA/DCM need to be resetted after power up or left alone as it comes up after the power and configuration is done?

If a reset is required, what are the requirements to satisfy the DCM so it goes to a lock state and release the system/IOs to a functional state?

Is it the same requirements for all Xilinx families of FPGA?

For a DCM to PLL_BASE, does the PLL require a reset? If yes... same characteristics as for the DCM? Reset active high for both?


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bassman59
Historian
Historian
12,040 Views
Registered: ‎02-25-2008

sparenteau1 wrote:
Hi all, I am new to this forum activities.

I am a little confused with two responses that looked conflicting to me. In one thread I read " Strictly speaking, you don't need to reset the FPGA after power-up." and in the above thread, I read: " Well, you DO realize that the DCM needs to be held reset until after its input clock is running?"

When you read, "the FPGA doesn't need a reset," that really means that "the storage elements in the FPGA (flip-flops, RAMs) are initialized -- reset -- as part of the configuration process, using a default value of '0' unless an initializer is specified in the user design." (whew!)

But, some specific features do need to be explicitly reset. One such feature is a DCM. If you want to ensure that a DCM or PLL will work properly, it needs to be reset whenever it is not locked. That includes at power-up, and also whenever the input clock stops or changes frequency. Search; there are many examples of how to reset a DCM. I presented one in this thread.

For a Spartan-6, does the FPGA/DCM need to be resetted after power up or left alone as it comes up after the power and configuration is done?

I would explicitly reset it.

If a reset is required, what are the requirements to satisfy the DCM so it goes to a lock state

Read The Fine Clocking User Guide. It's all there.

and release the system/IOs to a functional state?

Two separate issues. There is a configuration option that will cause the FPGA's configuration process to not complete (meaning: assertion of DONE and the two or three steps that follow that) until the DCMs are locked. One of those "steps" is taking the I/Os out of their configuration state (pulled up or floating, depending on HSWAPEN). If you disable that feature, the FPGA comes alive as soon as the configuration process is completed and if the DCMs don't lock until later, then you can still do other stuff.

Is it the same requirements for all Xilinx families of FPGA?

Never ever assume that. Always read the data sheets and the user guides for the specific device you're using. They can be highly similar yet differ in small but significant ways that will screw you.

For a DCM to PLL_BASE, does the PLL require a reset? If yes... same characteristics as for the DCM? Reset active high for both?

See above, and RTFM.

----------------------------Yes, I do this for a living.
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sparenteau1
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Registered: ‎02-21-2013

Thank you; this clarifies a lot of recent reading; not done yet...

 

The configuration option that you are refering to, is it the selection FALSE or TRUE in the directive of the DCM_SP or it is a selection embedded in the design tool like ISE?

 

      .STARTUP_WAIT("FALSE")                // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)

 

 

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bassman59
Historian
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8,642 Views
Registered: ‎02-25-2008


@sparenteau1 wrote:

Thank you; this clarifies a lot of recent reading; not done yet...

 

The configuration option that you are refering to, is it the selection FALSE or TRUE in the directive of the DCM_SP or it is a selection embedded in the design tool like ISE?

 

      .STARTUP_WAIT("FALSE")                // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)

 

 


Actually, it's in both places. When you instantiate the DCM, you have to set that generic/parameter to the state you want. In addition there is a bitgen ("Generate Programming File" in the GUI) option called "Wait for DLL lock" (in Startup options). 

 

Here's the rub. The doc for the "Wait for DLL lock" (which is "No Wait" by default) says that the startup phase will wait for the DLLs to lock. In typical circular Xilinx documentation fashion, it doesn't say what that really means. But read the Configuration Guide for the family you're using. In S3, the config guide shows a "sequence of events" in the configuration process, the last of which is "startup sequence." That last sequence has 7 phases. You can assign certain events, of which "wait for DCMs to lock," or LCK_cycle, is one, to any of these 7 phases, or have that feature skipped entirely. 

 

If you've did not set the LCK_cycle to anything other than the default (don't wait), then the parameter STARTUP_WAIT in the DCM is ignored. If LCK_cycle is set to a particular phase and no DCMs have the STARTUP_WAIT parameter set to TRUE then it doesn't wait. Finally, if the bitgen option is set to a particular phase and one or more DCMs have that parameter set to true, then the end of configuration will be held off until the DCMs lock.

 

Obviously if the DCM clock input isn't toggle when this is supposed to happen, the FPGA configuration will never complete and you'll be stuck.

----------------------------Yes, I do this for a living.
sparenteau1
Visitor
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8,642 Views
Registered: ‎02-21-2013

RTFM...seriously!!!
You not forced to answer, you do because you choose to do it. That does not give you any rights to be rude!!

Through the tons of documentation it is sometime difficult to see the main picture and grasp on the overall concept.
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bassman59
Historian
Historian
8,639 Views
Registered: ‎02-25-2008


@sparenteau1 wrote:
RTFM...seriously!!!
You not forced to answer, you do because you choose to do it. That does not give you any rights to be rude!!

Through the tons of documentation it is sometime difficult to see the main picture and grasp on the overall concept.

Should I delete the long response I just typed, the one which meant refreshing my memory by looking through a non-obvious FM and then (hopefully) clarifying it all for you, because you think I'm rude? Especially since you asked about specific characteristics of the DCM and PLL which are actually clearly answered in the relevant FM.

 

Please, give me a reason to help you.

----------------------------Yes, I do this for a living.
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sparenteau1
Visitor
Visitor
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Registered: ‎02-21-2013

This is very useful and could well explain the problem I am experiencing. Many selections of the similar options in many places...
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sparenteau1
Visitor
Visitor
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Registered: ‎02-21-2013

Leave it... I got the message to moderate my use of the forums. It was very useful to me and hopefully it will be to others. Your experienced view give confidence when in doubt.
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