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joe306
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Registered: ‎12-07-2018

Forwarded Clocks and Generated Clocks

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Hello, quick question about Forwarded Clocks and Generated Clocks.

My understanding of Forwarded Clocks is the an input clock comes into the FPGA, goes through a BUFG and then connects to an output pin. Another way would be for the input clock to directly connect to an ODDR and from the ODDR connect to the output pin. These are two examples of Forwarded Clocks.

Generated Clocks are clocks that are derived by a PLL or using Flip-flops. These clocks can be connected to output pins or also drive logic.

I guess one could say is that Forwarded Clocks have no change in frequency.

Question what about an SPI IP module where it generates a SCK clock output. That would be a Generated Clock and would need to be constrained, is that correct?

 

How does this sound, am I close?

Thank you

Joe

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Registered: ‎01-22-2015

@joe306 

Gosh!  Avrum’s complements kinda make me want to “call it a life” and retire.  -not sure things will get better.

Yes, when using the current Constraints Wizard, you must sometimes be smarter than the Wizard.  The Wizard is a work in progress which I am sure will develop into a very useful tool.

For the example circuit I have shown,  the Constraints Wizard in Vivado v2020.2 does not suggest anything under the “Generated Clocks” page.  However, under the “Forwarded Clocks” page, it shows the following suggested “Tcl Command”, which is same as the constraint that I suggested, except for the -name. 

Constr_Wiz_Fwd_Clock.jpg

So, in this particular example, you can probably follow the advice on the “Forwarded Clocks” page of the Constraints Wizard.

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5 Replies
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Registered: ‎01-22-2015

Hi Joe,

You are close.

A forwarded clock is term that is usually used with a source synchronous output interface.

In a source synchronous output interface, the FPGA sends clock and data to an external device (eg. a digital-to-analog converter (DAC)).

As you correctly mentioned, the ODDR is often used to send the forwarded clock out of the FPGA – as shown in the schematic below.
ODDR_FWD_CLK.jpg

Next, we use a constraint like the following to create a new clock (also called a generated clock) from an existing clock. 

create_generated_clock -name FCLK1 -source [get_pins ODDR1/C] -divide_by 1 [get_ports SSO1_CLK]

Specifically, the constraint does the following:

  • Names the generated clock as FCLK1
  • Identifies the source of FCLK1 as the clock that enters pin, C, of ODDR1
  • Indicates that FCLK1 has the same frequency as the source clock by using “-divide-by 1”
  • Identifies the pin/port, SSO1_CLK, as the point where the FCLK1 net starts.

This generated clock, FCLK1, will be the forwarded clock of the source synchronous output interface.  You will use the name, FCLK1, in set_output_delay constraints for the interface.

Cheers,
Mark

joe306
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Registered: ‎12-07-2018

Hello, thank you very much for responding to my post. I'm a little confused, if you run the Constraints Wizard you get opportunities to enter in constraints for Generated Clocks and Forwarded Clocks. In your example would you enter this twice? I can probably hear people grumble when I mention the Constraints Wizard since not many like it.

ConstraintsWiz.jpg

Thank you for helping me.

Joe

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avrumw
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Registered: ‎01-23-2009

This is another example of the Vivado Wizards trying to make things simpler, but actually making things more confusing. Mark's answer is correct - a "forwarded clock" is a system concept, and has no real meaning from a static timing point of view. In systems that use forwarded clocks, the output timing of these interfaces are often defined with respect to this forwarded clock, and hence we need to define the forwarded clock as a generated clock from the static timing point of view.

The wizard is just making it "easier" for you to visualize the system that you need to constrain by splitting the mechanism for creating generated clocks into two categories; one for generated clocks derived and used internally, and one for generated clocks that are only used for constraints in a clock forwarded system. But, in the end, they both use the create_generated_clock command.

So, given this (weird) way of how the wizards use the terminology, your original definitions seem more or less correct... But, I repeat, Mark's definitions are "more correct"!

Avrum

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Registered: ‎01-22-2015

@joe306 

Gosh!  Avrum’s complements kinda make me want to “call it a life” and retire.  -not sure things will get better.

Yes, when using the current Constraints Wizard, you must sometimes be smarter than the Wizard.  The Wizard is a work in progress which I am sure will develop into a very useful tool.

For the example circuit I have shown,  the Constraints Wizard in Vivado v2020.2 does not suggest anything under the “Generated Clocks” page.  However, under the “Forwarded Clocks” page, it shows the following suggested “Tcl Command”, which is same as the constraint that I suggested, except for the -name. 

Constr_Wiz_Fwd_Clock.jpg

So, in this particular example, you can probably follow the advice on the “Forwarded Clocks” page of the Constraints Wizard.

View solution in original post

joe306
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Registered: ‎12-07-2018

Thank you very much for helping me understand this Constraints Wizard.

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