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sms1955
Visitor
Visitor
7,858 Views
Registered: ‎12-12-2012

Frequency reduction from virtex 5 to virtex 6

Hi all,

I am new in VHDL programming and I hope to gain a lot from your experience.

 

I have a design in Virtex 5 working with maximum frequency of 220MHz. However, when I convert it to virtex 6 the frequency reduced by a huge amount and it was 30MHz only !!!!!!! Can anyone explain me why this happened.

Is it due licensing  issues or area or ..........

 

Please need your help ASAP

 

Thank you in advance.

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6 Replies
bassman59
Historian
Historian
7,856 Views
Registered: ‎02-25-2008


@sms1955 wrote:

Hi all,

I am new in VHDL programming and I hope to gain a lot from your experience.

 

I have a design in Virtex 5 working with maximum frequency of 220MHz. However, when I convert it to virtex 6 the frequency reduced by a huge amount and it was 30MHz only !!!!!!! Can anyone explain me why this happened.

Is it due licensing  issues or area or ..........

 

Please need your help ASAP

 

Thank you in advance.


Did you have a timing constraint set on each version of the design?

 

Also, since you are new: VHDL is not a programming language. You are not programming.

----------------------------Yes, I do this for a living.
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sms1955
Visitor
Visitor
7,852 Views
Registered: ‎12-12-2012

Thank you   for your reply and yes I kept the timimng constrain the same.

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avrumw
Guide
Guide
7,845 Views
Registered: ‎01-23-2009

Please post the timing report from the worst failing path. With that, we may be able to tell you what to look at next.

 

Avrum

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maynard1
Visitor
Visitor
7,811 Views
Registered: ‎11-26-2012

Hello there!

Well, from my humble experience I shows say that pin assignment is one the crucial art of FPGA performance. An improper pin assignment can always mess up your timing. I was working on a design that would not meet timing by no means. Changing optimization effort, place-route strategy brought be as close as 0.5ns to meeting my goal, but no success there.

Eventually the wire was the solution. When I routed the system clock to the correct pin with a wire, the project would compile even with the default settings and meet the timing closure easily. There is a reason why pin assignment is done in parallel to the board layout process, since one can hinder the other.

 

Regards

Sergej

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shaileshpa
Visitor
Visitor
7,746 Views
Registered: ‎03-26-2013

I also got same thing, in vertex 5 i got 202 mhz frequency , same i run on virtex 6 evalution board i got 0nly 51.02 mhz.

 

Can you explaine me why?

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avrumw
Guide
Guide
7,740 Views
Registered: ‎01-23-2009

You need to post the failing path - without that we can't help you.

 

One odd thing to note is that the default behavior of the timing engine changed between Virtex-5 and Virtex-6 when it comes to asynchronous preset/clear inputs of flip-flops. In V5 and earlier, these pins were not timed (it was if there was an implicit TIG on these pins). In V6 and onward they are timed. (The actual difference is that the reg_sr_r arc is enabled by default in V6 and onward). If you (for example) had the asynchronous preset/clear pin of a FF driven from a FF coming from another clock domain, this would be ignored in V5 but would cause a significant timing violation in V6.

 

Again, we need to see the failing path...

 

Avrum

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