Gateway Out Causing Timing Constraint Errors w/ HW-Cosim
FPGA: Spartan3E xc3s500e-5pq208
Before posting any code or model files, I was wondering if there is an easy explanation for this:
When compiling my System Generator model for Hardware Cosimulation, if I have no gateway out blocks (in order to view internal variables during cosim) I get no timing errors - infact my worst case slack is something like 17ns (my FPGA is 20ns clock).
When compiling for cosim WITH gateway out blocks, I get timing errors upstream from where I put the gateway outs. This is still the case when I use a delay block infront of the gateway out. The only way I can solve this timing error is by adding more latency to some of the blocks in my signal path, which is undesirable.
How is it that a Gateway Out (even with a delay block infront) would affect the signal path timing upstream, whereas the signal path normally meets timing very easily without the Gateway? Does the gateway out force some extra latency upstream that causes the signal to violate timing constraints? I couldn't find any documentation or forum posts that address this.