05-09-2019 08:58 AM
i am ameture designer , i am getting no clock warning in the following code
1. i am setting bit on posedge of lc signal
2. on neg edge of ec signal checking it and clearing it
i am getting no clock warning , can any body help me how to solve this problem what are consequences
module ec_dect (
input ec, // Clock
output reg end_of_frame // Asynchronous reset active low
//checking for lc signal
reg [2:0] count;
always@(posedge lc or negedge ec)
lc_bit = 1'b0;
if(ec == 1'b0)
count <= count +1;
lc_bit <= 0;
end_of_frame <= 1'b0;
end_of_frame <= 1'b1;
05-09-2019 09:18 AM
Hi, @chaitusvk ,
Do you create clock for your clock signal in XDC file?
05-09-2019 12:37 PM
The "no_clock" warning is because your "clock" is not constrained with a create_clock command in an XDC file.
But what is your "clock"?
This HDL description is not synchronous RTL - I am surprised the synthesis tool even took it without erroring out.
RTL synthesis can result in the inference of combinatorial logic, flip-flops or latches - that's it. No structural element in an FPGA (or ASIC), where there are only combinatorial logic, flip-flops and latches, can operate on both edges of a clock or on edges of different clocks. I have no idea what the synthesis tool ended up with here - probably something based on interconnected resettable latches...
Whatever this is, it is not recommended RTL design - it probably doesn't do what you want it to do (or at least won't when actually implemented in an FPGA) and will be impossible to properly constrain and therefore likely not useable as part of a larger system.
Whatever it is you are trying to do - this is not the way to do it...