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Visitor
Visitor
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Registered: ‎02-15-2019

Getting no clock warning in following code please correct me how to slove

Hi 

i am ameture designer , i am getting no clock warning in the following code 

1. i am setting bit on posedge of lc signal 

2. on neg edge of ec signal checking it and clearing it 

i am getting no clock warning , can any body help me how to solve this problem what are consequences

 

my code:

module ec_dect (
input ec, // Clock
input lc,
output reg end_of_frame // Asynchronous reset active low

);

//checking for lc signal
reg lc_bit;
reg [2:0] count;

always@(posedge lc or negedge ec)
begin
if(lc==1)
lc_bit = 1'b0;
else
begin

if(ec == 1'b0)
begin

if(lc_bit ==1)
begin
count <= count +1;
lc_bit <= 0;
end_of_frame <= 1'b0;
end
else
begin
end_of_frame <= 1'b1;
end

 

end
end
end

endmodule

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Highlighted
Moderator
Moderator
335 Views
Registered: ‎11-04-2010

Hi, @chaitusvk ,

Do you create clock for your clock signal in XDC file?

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Highlighted
Guide
Guide
314 Views
Registered: ‎01-23-2009

The "no_clock" warning is because your "clock" is not constrained with a create_clock command in an XDC file.

But what is your "clock"?

This HDL description is not synchronous RTL - I am surprised the synthesis tool even took it without erroring out.

RTL synthesis can result in the inference of combinatorial logic, flip-flops or latches - that's it. No structural element in an FPGA (or ASIC), where there are only combinatorial logic, flip-flops and latches, can operate on both edges of a clock or on edges of different clocks. I have no idea what the synthesis tool ended up with here - probably something based on interconnected resettable latches...

Whatever this is, it is not recommended RTL design - it probably doesn't do what you want it to do (or at least won't when actually implemented in an FPGA) and will be impossible to properly constrain and therefore likely not useable as part of a larger system.

Whatever it is you are trying to do - this is not the way to do it...

Avrum

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