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Visitor
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Registered: ‎05-21-2017

HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi,

 

I am using Vivado v2017.2(64bit) for implementing a Cortex Core on a Kintex KCU105 device. At the beginning, timing closure was always possible but after adding more and more peripherals I now ended up with some negative slacks in HOLD time analysis (intra-clock paths) - only located within one submodule of the core.

 

Violation with neg. slack of  -0.088 : 

The clock for source and destination flops comes from a MMCME3_ADV_X1Y2 . Interesting is that the path delay for the

source FF clock root (clkout3_buf/Q) is 

MMCME3_ADV_X1Y2 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
-3.363 -2.210 r fpga_pll/inst/mmcme3_adv_inst/CLKOUT2
net (fo=2, routed) 0.345 -1.865 fpga_pll/inst/clk55M_fpga_pll
BUFGCE_X1Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.075 -1.790 r fpga_pll/inst/clkout3_buf/O

 

whereas the path delay for the target FF (using the same clock root  clkout3_buf/Q) is

MMCME3_ADV_X1Y2 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
-3.838 -2.362 r fpga_pll/inst/mmcme3_adv_inst/CLKOUT2
net (fo=2, routed) 0.403 -1.959 fpga_pll/inst/clk55M_fpga_pll
BUFGCE_X1Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.083 -1.876 r fpga_pll/inst/clkout3_buf/O

 

The difference between the timing paths for common clock root instance is 1.790 - 1.876 =  -0.086  (that covers almost the slack of -0.088).  Both paths have the same instance - so I expect the timing to be identical at the output of this instance.

 

Q) Is this an error in the timing calculation ? 

 

Q) How to  solve the HOLD violations ?  I tried already implementation 

set_property -name {STEPS.POWER_OPT_DESIGN.ARGS.MORE OPTIONS} -value -hold_fix -objects [get_runs impl_1]

 but without success.

Q) Is there a possibility to delay specific datapath(s) by an attribute ?

 

br

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Visitor
Visitor
2,358 Views
Registered: ‎05-21-2017

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi Avrum,

 

thank you very much for the indication of the wrong clock structure.  Indeed, I found a control signal for bypassing clock gating in the processor core.

This did solve the HOLD issues.

 

best regards

Heinz

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi,

Vivado Timing analysis covers the all 4 process corners and report out the worst case.

So the difference of timing number in source and destination clock path is not a bug but the intended behavior to cover the all process corner (PVT variations).

Also as you mentioned that the clock path share the common path till the one specific point (i.e. clock root) and till that the numbers cannot be different which is true at hardware and to make it more realistic there is one term called clock pessimism.

Please read more about clock pessimism in below articles/ forum thread.

https://forums.xilinx.com/t5/Timing-Analysis/What-is-quot-clock-pessimism-quot/td-p/284876

https://www.xilinx.com/support/answers/50450.html

Thanks,
Yash
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Guide
Guide
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Registered: ‎01-23-2009

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Here is another post that describes clock pessimism.

 

Avrum

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Visitor
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Registered: ‎05-21-2017

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi Yash and Avrum,

 

thank you for your answers. I now understand the pessimism used in the calculation.

 

But how can I constrain the design or control the design flow to avoid such HOLD time violations.

Can I somehow add a delay into the affected datapaths ?

Why does -hold_fix not fix these violations ?

 

thanks and best regards

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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But how can I constrain the design or control the design flow to avoid such HOLD time violations.

 

In a nutshell, you can't...

 

By default, the tools fix hold time. If they can't fix them, then there is a reason they can't fix them - something about the design, not a tool option.

 

So first. Let's make sure that the timing report you are looking at is after place and route (implementation) and not just after synthesis. Hold times are fixed in the route stage, and hence it is normal to see small hold time violations after synthesis - the router will fix them.

 

If these are after place and route, then I can't explain them. There is no reason that I know of that the tools would be unable to fix a hold time between flip-flops on the same clock.

 

Avrum

 

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Visitor
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Registered: ‎05-21-2017

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi Avrum,

thank you for yout explanations.

 

I re-tried the implementation with several options and strategies. However the HOLD problems became even worse. 

So I tied not find any solution so far. 

 

Best regards

Heinz 

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Guide
Guide
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Registered: ‎01-23-2009

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Please post the detailed timing report for the failing path.

 

Avrum

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Observer
Observer
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Registered: ‎08-17-2016

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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If it is not a design issue, you might need to try more settings. Usually, some of the builds will not have hold timing issues.

----------------------------------------------------
InTime - Timing Optimization with ML (Blog)
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Visitor
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Registered: ‎05-21-2017

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi Avrum,

 

please find attached the 2 violated paths (all other slacks were met)

 

br

Heinz

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Guide
Guide
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Registered: ‎01-23-2009

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Your clock structure is incorrect.

 

On the destination flip-flop, the clock does not go directly from the MMCM through a BUFGCE to the flip-flop, but instead goes

 

MMCM -> BUFGCE -> LUT -> BUFGCE -> destination flip-flop

 

It is this LUT and extra BUFGCE that are causing the timing violation. And you will not be able to get it to meet timing with this clock structure; you need to remove this LUT and extra BUFGCE from the destination clock.

 

Avrum

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Visitor
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Registered: ‎05-21-2017

Re: HOLD violation - Error in timing calculation ? - And how to fix (manually) ?

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Hi Avrum,

 

thank you very much for the indication of the wrong clock structure.  Indeed, I found a control signal for bypassing clock gating in the processor core.

This did solve the HOLD issues.

 

best regards

Heinz

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