UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor dominduke
Visitor
475 Views
Registered: ‎07-04-2018

Help Carry LookAhead vs Ripple Carry

Jump to solution
Hello,
I have implemented 3 combinational circuits of adders (RCA, CLA and IP CORE, adder v.12) in a method to measure the power consumption in the FPGA, but the results in the delays are incoherent.
A ripple carry should be slower than a lookahead however in my results it is not appreciated. I have checked it for different size for the entries.
I leave an image, so you can give me your conclusions.
Thanks for your help. P.S. The delay I have taken from a circuit that implements a frequency of 25MHz, and I have taken calculations from the term WNS. (Implementation -> Report Timming)
25MHz = 40ns -> DELAY= 40ns - WNS
Vivado 2017.1

 

Captura.JPG
0 Kudos
1 Solution

Accepted Solutions
Guide avrumw
Guide
380 Views
Registered: ‎01-23-2009

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution

All of this discussion is probably meaningless...

When RTL is synthesized, the synthesis tool translates the RTL to a netlist and then optimizes the netlist. All of these "architectures" differ only in how the combinatorial logic is implememented, and since synthesis is designed to optimize a combinatorial network to the fastest/smallest amount of logic, the majority of the difference between these architectures will be removed. In the end, you may end up with similar performance from all of them, or variations that are more dependent on how well the synthesis tool identified the "best" implementation.

Finally, there is a clear answer to this question - the fastest is simply to use the "+" operator. Xilinx FPGAs have dedicated carry chains (which are 4 or 8 bit fast lookahead carry blocks) which are used automatically when the addition operator is used. This will be, by far, the fastest and smallest implementation of addition.

Avrum

View solution in original post

5 Replies
Scholar u4223374
Scholar
435 Views
Registered: ‎04-26-2015

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution

The short answer is that Vivado doesn't do timing like you're expecting. Vivado will optimize timing until it passes, and then stop. For a very simple task like a 25MHz adder, it's very likely to take a first rough guess at laying out the design, see that it passes timing, and then skip any further optimization. As a result, using the WNS to compare timing is not very meaningful.

 

I'm not aware of a good way to make Vivado do what you want.

 

Visitor dominduke
Visitor
410 Views
Registered: ‎07-04-2018

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution


I mean because of the implementations that Vivado performs. I can not get exact conclusions. Could I check this in some way? schematic for example? Thanks.
0 Kudos
Guide avrumw
Guide
381 Views
Registered: ‎01-23-2009

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution

All of this discussion is probably meaningless...

When RTL is synthesized, the synthesis tool translates the RTL to a netlist and then optimizes the netlist. All of these "architectures" differ only in how the combinatorial logic is implememented, and since synthesis is designed to optimize a combinatorial network to the fastest/smallest amount of logic, the majority of the difference between these architectures will be removed. In the end, you may end up with similar performance from all of them, or variations that are more dependent on how well the synthesis tool identified the "best" implementation.

Finally, there is a clear answer to this question - the fastest is simply to use the "+" operator. Xilinx FPGAs have dedicated carry chains (which are 4 or 8 bit fast lookahead carry blocks) which are used automatically when the addition operator is used. This will be, by far, the fastest and smallest implementation of addition.

Avrum

View solution in original post

Teacher drjohnsmith
Teacher
367 Views
Registered: ‎07-09-2009

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution

as @avrumw says, you have th eanswer, let the tools do their thing.

 

In th egood old days of the 1980's, when a lot of books were written, people looked at how to make real logic chips such as 74163 , work fast, and ideas such as fast carry, ripple carry et all were the norm.

 

Think of it like programing, once upon a time , we all had tricks for doing things like fast multiply by 31,

     or asm code, but now, the C compiler does a bteer job than I could and knows more tricks.

 

Same in HDL, ish.

    the tools know many tricks of how to optimise the system for your code,  many many more than you could.

   

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Teacher drjohnsmith
Teacher
365 Views
Registered: ‎07-09-2009

Re: Help Carry LookAhead vs Ripple Carry

Jump to solution

Oh, and if your teacher argues with you, point them at me ......  :->

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>