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Explorer
Explorer
985 Views
Registered: ‎09-28-2012

Help on verilog timing constraint

Hello,

When I read timing constraint, the verilog example is not clear enough to me. In the below picture, which clock signal is identified as clock after the line:

 

*** (* clock_signal = "yes" *)

 

If the three signals are all identified as clock, how can they?

 

wire clk_0;

wire clk_90;

wire clk_200;

 

Whether signals connected to a DFF clock pins are all affected by the above '*** line?

 

 

Thanks,

 

 

 

timing_verilog.PNG

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3 Replies
Historian
Historian
975 Views
Registered: ‎01-23-2009

Re: Help on verilog timing constraint

So, first, this is not a timing constraint. In fact, I have no idea what it is or where it comes from.

 

The (* *) syntax is for defining an attribute in Verilog. An attribute is some information passed in the Verilog file that is not part of the language, but that provides some tool specific information to some too. Traditionally this has been used to pass information to the synthesis/implementation tools; the syntax of the Verilog languages only covers simulation - the rest of the stuff that we do with it (HDL synthesis, etc... ) are not part of the language.

 

So this line is attaching the "clock_signal" attribute with a value of "yes" to the thing it precedes - like other Verilog constructs, it ends at the first semicolon. It would have been clearer to write

 

(* clock_signal = "yes" *) wire  clk_0;

wire clk_90;

wire clk_180;

 

So only the wire clk_0 has the attribute set.

 

But again, I know of no tool (at least in the Xilinx tool set) that pays any attention to an attribute called "clock_signal".

 

Avrum

Explorer
Explorer
970 Views
Registered: ‎09-28-2012

Re: Help on verilog timing constraint

Thank you for your reply. A lot of info is given from you writing.

But it is still a surprise to me that 

 

 I know of no tool (at least in the Xilinx tool set) that pays any attention to an attribute called "clock_signal".

 

The snippet is copied from UG612 v14.3, page 88. This is a Xilinx document.

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Voyager
Voyager
957 Views
Registered: ‎06-20-2017

Re: Help on verilog timing constraint

If a clock signal goes through combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify which input pin or internal signal is the real clock signal.  The CLOCK_SIGNAL constraint allows you to define the clock signal.
 
This appears to be for instances (that are not recommended) when somebody is creating a gated clock using a LUT, e.g., assign clk = iCLK & iCE, in ISE.  Since doing this is a bad practice, I was not familiar with this either.  But if you insist on doing this, this will let the tool know your signal named iCLK, and not iCE, is the actual clock.

Adaptable Processing coming to an IP address near you.