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Visitor fball
Visitor
5,917 Views
Registered: ‎07-15-2015

Helping to Meet Timing on the Reset of a FIFO With Two Clocks

HI.

 

I have a Virtex-7 -3 design which uses about 31% of the BRAMs and 36% FFs. Not particularly heavy. I run the board at 240MHz, this includes the i/o and general interfaces. I have a sort algorithm in the centre which I want to run at 480MHz to dramatically increase my efficiency. The majority of BRAMs and FFs are used in this sort. The reset line gets held high for 5 clks, with a 2 clk wait before data enters.

 

I have a condition that the algorithm must be reset every N clock cycles (it is currently hardcoded at around 250clks in the 250MHz domain). From this you can see the reset line entering my algorithm is running on the slower clock. The reset is heavily pipelined with minimal fanout. The reset pipe is then registered before it hits the FIFO meaning it has a fanout of 1 at this stage. It works and meets timing for all the FIFOs which only run on one clock domain. For the FIFOs which have different read / write clocks, this is where I hit issues. It fails timing, especially on my "output" buffers whereby the write clock is 480MHz and the read clock is 240MHz.

 

I've tried registering the reset line before it hits the FIFO on either the slow or fast clock with minimal difference. I seem to get killed by "clock uncertainty". You can see how close the register is in the photo. In this version I've registered the reset on the fast clock before it hits the FIFO. 

Have you any tips on how I can help meet timing, anything I can do to help, or something I should be doing differently?


The 

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6 Replies
Moderator
Moderator
5,800 Views
Registered: ‎01-16-2013

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

Hi,

There should be the constraint for this path and it should not falls under *async_default*
Please refer https://forums.xilinx.com/t5/Timing-Analysis/Ignore-timing-analysis-of-async-FIFO-reset-set-max-delay/td-p/694409 which describe the similar application of timing analysis on FIFO.

Thanks,
Yash
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Historian
Historian
5,787 Views
Registered: ‎01-23-2009

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

The RST input to the FIFO36E1 is documented as being asynchronous. From UG473 (v1.12), table 2-3, the description of RST:

 

Asynchronous reset of all FIFO functions, flags, and
pointers. RST must be asserted for five read and write clock
cycles. 7 series FPGAs block RAMs have a synchronizer not
present in previous FPGA architectures that has simplified
the reset function.

 

As a result, the path that ends at the RST input to the FIFO36E1 can be declared false:

 

set_false_path -to [get_pins payload/pp_top/out_buffer[*].bram_fifo/RST]

 

Avrum

Visitor fball
Visitor
5,760 Views
Registered: ‎07-15-2015

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

This isn't so clear in the manual as I would have expected. 

- Exactly which clock the timing specs for reset apply to?

- Whether it is guaranteed-safe to apply a false path constraint to the reset line?

- By safe, meaning, no possibility of incorrect reset or metastability problems?

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Historian
Historian
5,750 Views
Registered: ‎01-23-2009

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

It's "pretty clear"...

 

"7 series FPGAs block RAMs have a synchronizer not present in previous FPGA architectures that has simplified the reset function"

 

This means that the RST input is internally synchronized by the FIFO. This is consistent with the fact that the RST must be asserted for 5 clock cycles, since it needs that time to get through the internal synchronizers.

 

You have to remember that the FIFO has two modes - synchronous and asynchronous. When in synchronous mode, both clocks are the same. In this mode, the synchronizers for the empty/full generation are disabled (which results in the shorter flag deassertion latencies) - presumably the reset synchronizer is disabled as well (I don't know this for a fact). In this case, we end up with setup/hold checks of the RST with respect to both RDCLK and WRCLK (which are the same clock).

 

In asynchronous mode (where the RDCLK and WRCLK are asynchronous), there is logic on both domains that need to be reset. So one single reset can't be used for all the logic. Instead of providing a RDRST and a WRRST, Xilinx provides a single asynchronous reset which is internally synchronized to both domains.

 

So, for your three questions:

 

- Exactly which clock the timing specs for reset apply to?

 

Both. Which means in asynchronous mode they cannot be met (since the two clocks are asynchronous). This can only make sense in synchronous mode where both clocks are the same clock.

 

- Whether it is guaranteed-safe to apply a false path constraint to the reset line?

 

"Guaranteed" is a tough word, but I believe it is the right thing to do. If you want, you can always do a "set_max_delay -datapath_only" instead of set_false_path - this will just limit the latency of the reset. But from your own analysis, it is impossible to meet timing on both domains, so you have no choice but to override the normal setup/hold checks.

 

- By safe, meaning, no possibility of incorrect reset or metastability problems?

 

Again, it explicitly says that there is an internal synchronizer. I have to assume that this synchronizer is designed correctly and deals with metastability properly (and I have every reason to believe this is the case).

 

Avrum

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Xilinx Employee
Xilinx Employee
5,730 Views
Registered: ‎05-07-2015

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

HI @fball

 

The FIFO reset requirements are simplified in 7 series FPGAs. The FIFO reset assertion is now synchronized to the read and write clocks. However, the reset deassertion is still asynchronous.

refer page 9 of UG473

 

 

Thanks
Bharath
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Historian
Historian
5,713 Views
Registered: ‎01-23-2009

Re: Helping to Meet Timing on the Reset of a FIFO With Two Clocks

@nagabhar,

 

I am not sure what you mean by "However, the reset deassertion is still asynchronous."

 

The RST input is asynchronous (both assertion and deassertion). This is synchronized internally to the FIFO block to ensure that logic on both domains resets cleanly as long as the RST is asserted for at least 5 clock cycles (presumably of the slower clock domain).

 

Avrum

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