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Adventurer
Adventurer
11,621 Views
Registered: ‎01-15-2013

High performance design practices

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Hi,

 

I read that in Xilinx FPGA design, a reset is redundant unless there is a feedback as there is GSR present in the FPGA that makes all the flip-flop into a known state.

 

I also read that inorder to use the in-built DSP slices and BRAM, it should have a synchronous reset. However, to use a serial shift register (SRL) there should not be a reset. 

 

Suppose my design uses BRAM, DSP and SRL, I am confused whether I should really have a reset in my RTL or not???Could anyone clarify my doubts.

 

Thank you.

 

regards,

Paul

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Participant isaakian
Participant
19,334 Views
Registered: ‎07-03-2013

Re: High performance design practices

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The tools dont require you to use a reset in your RTL to infer block-rams, or DSPs.  Although there is limited support for synchronous resets on the output flop stage(s) you can usually design safely without them.  

 

As long as your control structures (e.g. Finite state machines or other control processes) use resets and/or enables to correctly capture and qualify when data is valid, you can avoid using resets in most datapath logic.  Typically this requires you to only initilaize (reset) the input stage to pipeline logic, or to run a preset at startup to get a known internal state.

 

By avoiding resets in the pipeline datapath for DSPs and other LUT based math functions, you can significantly reduce the number of control sets and routing resources required, allowing a much higher operating frequency.  

 

The exact details of course depends on your design.  Note however, relying on the GSR by itself is rarely viable as you almost always have FSMs or other logic that needs to be reset to a known valid starting state synchronously during both starutp and during operational conditions (e.g. software based reset of hardware datapath etc).

 

Digital Design Golden Rule: If its not tested - its broken.

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5 Replies
Scholar austin
Scholar
11,613 Views
Registered: ‎02-27-2008

Re: High performance design practices

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Go read Ken Chapman's excellent treatise on reset:

 

www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
11,609 Views
Registered: ‎01-15-2013

Re: High performance design practices

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Hi Austin,

Thank you for the reply.

 

I have already read this document and I totally understand the global reset now. My question is if I don't have a reset in my design, would the tool infer BRAM and DSP slices automatically from RTL (Its mentioned that BRAM and DSP slices both require synchronous reset) ?

 

regards,

Paul

 

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Teacher rcingham
Teacher
11,592 Views
Registered: ‎09-09-2010

Re: High performance design practices

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On the other hand:
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Participant isaakian
Participant
19,335 Views
Registered: ‎07-03-2013

Re: High performance design practices

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The tools dont require you to use a reset in your RTL to infer block-rams, or DSPs.  Although there is limited support for synchronous resets on the output flop stage(s) you can usually design safely without them.  

 

As long as your control structures (e.g. Finite state machines or other control processes) use resets and/or enables to correctly capture and qualify when data is valid, you can avoid using resets in most datapath logic.  Typically this requires you to only initilaize (reset) the input stage to pipeline logic, or to run a preset at startup to get a known internal state.

 

By avoiding resets in the pipeline datapath for DSPs and other LUT based math functions, you can significantly reduce the number of control sets and routing resources required, allowing a much higher operating frequency.  

 

The exact details of course depends on your design.  Note however, relying on the GSR by itself is rarely viable as you almost always have FSMs or other logic that needs to be reset to a known valid starting state synchronously during both starutp and during operational conditions (e.g. software based reset of hardware datapath etc).

 

Digital Design Golden Rule: If its not tested - its broken.

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Scholar markcurry
Scholar
11,584 Views
Registered: ‎09-16-2009

Re: High performance design practices

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BRAMs do NOT require synchronous resets - in fact you can NOT use resets of any kind to infer a BRAM.

For BRAM inference, see the section in the XST users guide and follow it closely.

 

It's almost the same case with DSP48s - here you can have some resets.  Again see the XST users guide.

 

Regards,

 

Mark

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